Logic cell array and bus system

• US 8,058,899 B2
• Filed: 02/13/2009
• Issued: 11/15/2011
• Est. Priority Date: 10/06/2000
• Status: Expired due to Fees

• Current Assignee: Scientia Sol Mentis AG (PACT XPP Schweiz AG)
• Original Assignee: Maren Krass, Thomas Richter
• Inventors: Vorbach, Martin, Ehlers, Gerd, Reichardt, Dirk, May, Frank, Lier, Frank, Rao, Prashant, Baumgarte, Volker, Oertel, Jens, Nückel, Armin
• Primary Examiner(s): Tan; Vibol
• Application Number:
  US12/371,040
• Publication Number:
  US 20090146691A1
• Time in Patent Office: 1,005 Days
• Field of Search: 326 38- 41, 708/490, 708/503, 708/505, 708/620, 708/670
• US Class Current: 326/39
• CPC Class Codes: G06F 13/4022 using switching circuits, e.g. switching matrix, connection or expansion network G06F13/4009 takes precedence
• CPC Class Codes: G06F 13/4027 using bus bridges G06F13/4022 takes precedence
• CPC Class Codes: G06F 15/7825 Globally asynchronous, locally synchronous, e.g. network on chip
• CPC Class Codes: G06F 15/7867 with reconfigurable architecture
• CPC Class Codes: G06F 15/80 comprising an array of processing units with common control, e.g. single instruction multiple data processors G06F15/82 takes precedence ; for correlation function computation G06F17/15
• CPC Class Codes: G06F 15/8023 Two dimensional arrays, e.g. mesh, torus
• CPC Class Codes: G06F 15/8092 Array of vector units
• CPC Class Codes: G06F 15/82 data or demand driven
• CPC Class Codes: G06F 9/3001 Arithmetic instructions
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A logic cell array having a number of logic cells and a segmented bus system for logic cell communication, the bus system including different segment lines having shorter and longer segments for connecting two points in order to be able to minimize the number of bus elements traversed between separate communication start and end points.

Claims

1. A configurable computing processor chip comprising:

configurable elements for configurably processing data, the configurable elements being arranged in an array and being interconnected via a configurable interconnect system, the array comprising;

a plurality of programmable gate array (PGA) elements;

a plurality of dedicated multi-bit ALU elements each having at least one multi-bit adder and one multi-bit multiplier and being configurable in function; and

a plurality of multi-bit configurable RAM elements, wherein the RAM elements receive data and address information from the configurable interconnect system and send output data directly to the configurable interconnect system; and

at least one configurable multi-bit IO function unit communicatively coupled to the array.

2. The configurable computing processor chip according to claim 1, wherein the interconnect system is a segmented operand data interconnect system.

3. The configurable computing processor chip according to claim 2, wherein the interconnect system comprises short segments and long segments crossing multiple short segments.

4. The configurable computing processor chip according to claim 1, wherein the at least one configurable multi-bit IO function unit is adapted for allowing interfacing to at least one of a memory and a peripheral.

5. The configurable computing processor chip according to claim 4, wherein at least one of the at least one IO function unit comprises at least a multi-bit write data input and a multi-bit read data output.

10. The configurable computing processor chip according to claim 1, wherein at least one of the plurality of RAM elements has at least one read address input, at least one write address input, at least one data input, and at least one data output.

11. The configurable computing processor chip according to claim 1, wherein an ALU of each of at least one of the plurality of ALU elements has at least 3 data inputs at least for processing a multiply-add operation.

12. The configurable computing processor chip according to claim 11, wherein at least one of the plurality of ALU elements comprises at least one registered data input from the configurable interconnect system.

13. The configurable computing processor chip according to claim 12, wherein at least one of the plurality of ALU elements comprises at least one registered data output.

20. The configurable computing processor chip according to any one of claims 1 and 10, wherein the plurality of RAM elements are arranged in at least one row within the array.

44. The configurable computing processor chip of claim 1, wherein the configurable elements are runtime configurable.

68. The configurable computing processor chip according to claim 1, wherein the at least one configurable multi-bit IO function unit is configurable in at least one of function and interconnection.

69. The configurable computing processor chip according to claim 1, wherein the IO function unit is connected to the configurable interconnect system.

70. The configurable computing processor chip according to claim 1, wherein the IO function unit is connected directly to the configurable interconnect system.

81. The configurable computing processor chip according to claim 1, wherein an ALU of each of at least one of the plurality of ALU elements has at least 4 data inputs at least for simultaneously processing two additions and one accumulation.

82. The configurable computer processor chip according to anyone of claims 1, 6, 21, 26, and 45, wherein the RAM elements are addressable on the configurable interconnect system separately from the plurality of multi-bit ALU elements.

6. A configurable computing processor chip comprising:

configurable elements for configurably processing data, the configurable elements being arranged in an array and being interconnected via a configurable interconnect system, the array comprising;

a plurality of programmable gate array (PGA) elements;

a plurality of dedicated multi-bit ALU elements each having at least one multi-bit adder and one multi-bit multiplier and being configurable in function; and

a plurality of multi-bit configurable RAM elements, wherein the RAM elements receive data and address information from the configurable interconnect system and send output data directly to the configurable interconnect system; and

at least one configurable multi-bit IO function unit communicatively coupled to the array;

wherein;

the at least one configurable multi-bit IO function unit is adapted for allowing interfacing to at least one of a memory and a peripheral;

at least one of the at least one IO function unit comprises at least a multi-bit write data input and a multi-bit read data output; and

at least one of the at least one IO function unit comprises an arrangement for synchronizing a data transfer.

7. The configurable computing processor chip according to claim 6, wherein at least one of the at least one IO function unit has at least an address interface.

8. The configurable computing processor chip according to any one of claims 6 and 7, wherein at least one of the at least one IO function unit is located physically close to an edge of the array.

9. The configurable computing processor chip according to claim 6, wherein at least one of the plurality of RAM elements has at least one read address input, at least one write address input, at least one data input, and at least one data output.

38. The configurable computing processor chip according to claim 9, wherein the plurality of RAM elements are arranged in at least one row within the array.

65. The configurable computing processor chip according to claim 6, wherein an ALU of each of at least one of the plurality of ALU elements has at least 3 data inputs.

66. The configurable computing processor chip according to claim 6, wherein the at least one configurable multi-bit IO function unit is configurable in at least one of function and interconnection.

73. The configurable computing processor chip according to claim 6, wherein the IO function unit is connected to the configurable interconnect system.

74. The configurable computing processor chip according to claim 6, wherein the IO function unit is connected directly to the configurable interconnect system.

14. A configurable computing processor chip comprising:

configurable elements for configurably processing data, the configurable elements being arranged in an array and being interconnected via a configurable interconnect system, the array comprising;

a plurality of programmable gate array (PGA) elements;

a plurality of dedicated multi-bit ALU elements each having at least one multi-bit adder and one multi-bit multiplier and being configurable in function; and

a plurality of multi-bit configurable RAM elements; and

at least one configurable multi-bit IO function unit communicatively coupled to the array;

wherein;

at least one of the plurality of ALU elements has at least 3 data inputs;

at least one of the plurality of ALU elements comprises at least one registered data input from the configurable interconnect system;

at least one of the plurality of ALU elements comprises at least one registered data output; and

at least one of the plurality of ALU elements comprises multiple input register stages.

63. The configurable computing processor chip according to claim 14, wherein, for the at least one of the plurality of ALU elements having the at least 3 data inputs, an ALU of each of the at least one of the plurality of ALU elements has the at least 3 data inputs.

15. A configurable computing processor chip comprising:

configurable elements for configurably processing data, the configurable elements being arranged in an array and being interconnected via a configurable interconnect system, the array comprising;

a plurality of programmable gate array (PGA) elements;

a plurality of dedicated multi-bit ALU elements each having at least one multi-bit adder and one multi-bit multiplier and being configurable in function; and

a plurality of multi-bit configurable RAM elements; and

at least one configurable multi-bit IO function unit communicatively coupled to the array;

wherein;

at least one of the plurality of ALU elements has at least 3 data inputs;

at least one of the plurality of ALU elements comprises at least one registered data input from the configurable interconnect system;

at least one of the plurality of ALU elements comprises at least one registered data output; and

the plurality of ALU elements includes an ALU element that comprises at least one output register adapted for receiving a result of said ALU element and connectable for allowing output of the output register to be fed back for further processing within said ALU element.

16. The configurable computing processor chip according to claim 15, wherein at least one of the plurality of ALU elements comprises at least 2 data outputs.

62. The configurable computing processor chip according to claim 15, wherein, for the at least one of the plurality of ALU elements having the at least 3 data inputs, an ALU of each of the at least one of the plurality of ALU elements has the at least 3 data inputs.

17. A configurable computing processor chip comprising:

configurable elements for configurably processing data, the configurable elements being arranged in an array and being interconnected via a configurable interconnect system, the array comprising;

a plurality of programmable gate array (PGA) elements;

a plurality of dedicated multi-bit ALU elements each having at least one multi-bit adder and one multi-bit multiplier and being configurable in function; and

a plurality of multi-bit configurable RAM elements; and

at least one configurable multi-bit IO function unit communicatively coupled to the array;

wherein;

at least one of the plurality of ALU elements has at least 3 data inputs;

at least one of the plurality of ALU elements comprises at least one registered data input from the configurable interconnect system;

at least one of the plurality of ALU elements comprises at least one registered data output; and

at least one of the plurality of ALU elements comprises at least two status outputs to the interconnect system.

18. The configurable computing processor chip according to claim 17, wherein at least one of the plurality of ALU elements comprises at least one control input from the interconnect system.

19. The configurable computing processor chip according to claim 17, wherein the plurality of ALU elements are arranged in at least one row within the array.

39. The configurable computing processor chip according to claim 19, wherein the plurality of RAM elements are arranged in at least one row within the array.

61. The configurable computing processor chip according to claim 17, wherein, for the at least one of the plurality of ALU elements having the at least 3 data inputs, an ALU of each of the at least one of the plurality of ALU elements has the at least 3 data inputs.

21. A configurable computing processor chip comprising:

configurable elements arranged in an array;

at least one configurable multi-bit IO function unit communicatively coupled to the array; and

a configurable interconnect system interconnecting the configurable elements;

wherein;

at least some of the configurable elements are organized in rows within the array, each of the configurable elements inside a row comprising at least one connect into the configurable interconnect system;

the array includes a plurality of programmable gate array (PGA) elements, at least one row of ALU elements and at least two rows of RAM elements; and

the RAM elements receive data and address information from the configurable interconnect system and send output data directly to the configurable interconnect system.

22. The configurable computing processor chip according to claim 21, wherein the interconnect system is a segmented operand data interconnect system.

23. The configurable computing processor chip according to claim 22, wherein the interconnect system comprises short segments and long segments crossing multiple short segments.

24. The configurable computing processor chip according to claim 21, wherein the at least one IO function unit interfaces to at least one of a memory and a peripheral.

25. The configurable computing processor chip according to claim 24, wherein at least one of the at least one IO function unit comprises at least a multi-bit write data input and a multi-bit read data output.

29. The configurable computing processor chip according to claim 21, wherein at least one of the RAM elements has at least one read address input, at least one write address input, at least one data input, and at least one data output.

30. The configurable computing processor chip according to claim 21, wherein an ALU of each of at least one of the ALU elements has at least 3 data inputs.

31. The configurable computing processor chip according to claim 30, wherein at least one of the ALU elements comprises at least one registered data input from the configurable interconnect system.

32. The configurable computing processor chip according to claim 31, wherein at least one of the ALU elements comprises at least one registered data output.

41. The configurable computing processor chip of claim 21, wherein the ALU elements and the RAM elements are some of the configurable elements of the array.

60. The configurable computing processor chip according to claim 21, wherein the at least one configurable multi-bit IO function unit is configurable in at least one of function and interconnection.

75. The configurable computing processor chip according to claim 21, wherein the IO function unit is connected to the configurable interconnect system.

76. The configurable computing processor chip according to claim 21, wherein the IO function unit is connected directly to the configurable interconnect system.

26. A configurable computing processor chip comprising:

configurable elements arranged in an array;

a configurable interconnect system interconnecting the configurable elements; and

at least one IO function unit for interfacing to at least one of a memory that is external to the processor chip and a peripheral device;

wherein;

at least some of the configurable elements are organized in rows within the array, each of the configurable elements inside a row comprising at least one connect into the configurable interconnect system;

the array includes a plurality of gate array (PGA) elements, at least one row of ALU elements and at least two rows of RAM elements, wherein the RAM elements receive data and address information from the configurable interconnect system and send output data directly to the configurable interconnect system;

at least one of the at least one IO function unit comprises at least a multi-bit write data input and a multi-bit read data output; and

at least one of the at least one IO function unit, comprises an arrangement for synchronizing a data transfer.

27. The configurable computing processor chip according to claim 26, wherein at least one of the at least one IO function unit has at least an address interface.

28. The configurable computing processor chip according to any one of claims 26 and 27, wherein at least one of the at least one IO function unit is located physically close to an edge of the array.

40. The configurable computing processor chip according to claim 26, wherein at least one of the RAM elements has at least one read address input, at least one write address input, at least one data input, and at least one data output.

57. The configurable computing processor chip according to claim 26, wherein an ALU of each of at least one of the plurality of ALU elements has at least 3 data inputs.

58. The configurable computing processor chip according to claim 26, wherein the at least one IO function unit is configurable in at least one of function and interconnection.

77. The configurable computing processor chip according to claim 26, wherein the IO function unit is connected to the configurable interconnect system.

78. The configurable computing processor chip according to claim 26, wherein the IO function unit is connected directly to the configurable interconnect system.

33. A configurable computing processor chip comprising:

configurable elements arranged in an array; and

a configurable interconnect system interconnecting the configurable elements;

wherein;

at least some of the configurable elements are organized in rows within the array, each of the configurable elements inside a row comprising at least one connect into the configurable interconnect system;

the array includes at least one row of ALU elements and at least two rows of RAM elements;

at least one of the ALU elements has at least 3 data inputs;

at least one of the ALU elements comprises at least one registered data input from the configurable interconnect system;

at least one of the ALU elements comprises at least one registered data output; and

the ALU elements comprise an ALU element that comprises at least one output register adapted for receiving a result of said ALU element and connectable for allowing output of the output register to be fed back for further processing within said ALU element.

34. The configurable computing processor chip according to claim 33, wherein at least one of the ALU elements comprises at least 2 data outputs.

55. The configurable computing processor chip according to claim 33, wherein, for the at least one of the plurality of ALU elements having the at least 3 data inputs, an ALU of each of the at least one of the plurality of ALU elements has the at least 3 data inputs.

35. A configurable computing processor chip comprising:

configurable elements arranged in an array; and

a configurable interconnect system interconnecting the configurable elements;

wherein;

at least some of the configurable elements are organized in rows within the array, each of the configurable elements inside a row comprising at least one connect into the configurable interconnect system;

the array includes at least one row of ALU elements and at least two rows of RAM elements;

at least one of the ALU elements has at least 3 data inputs;

at least one of the ALU elements comprises at least one registered data input from the configurable interconnect system;

at least one of the ALU elements comprises at least one registered data output; and

at least one of the ALU elements comprises at least two status outputs to the interconnect system.

36. The configurable computing processor chip according to claim 35, wherein at least one of the ALU elements comprises at least one control input from the interconnect system.

54. The configurable computing processor chip according to claim 35, wherein, for the at least one of the plurality of ALU elements having the at least 3 data inputs, an ALU of each of the at least one of the plurality of ALU elements has the at least 3 data inputs.

37. A configurable computing processor chip comprising:

configurable elements arranged in an array; and

a configurable interconnect system interconnecting the configurable elements;

wherein;

at least some of the configurable elements are organized in rows within the array, each of the configurable elements inside a row comprising at least one connect into the configurable interconnect system;

the array includes at least one row of ALU elements and at least two rows of RAM elements;

at least one of the ALU elements has at least 3 data inputs;

at least one of the ALU elements comprises at least one registered data input from the configurable interconnect system;

at least one of the ALU elements comprises at least one registered data output; and

at least one of the ALU elements comprises multiple input register stages.

53. The configurable computing processor chip according to claim 37, wherein, for the at least one of the plurality of ALU elements having the at least 3 data inputs, an ALU of each of the at least one of the plurality of ALU elements has the at least 3 data inputs.

42. A configurable computing processor chip comprising:

configurable elements for configurably processing data, the configurable elements being arranged in an array and being interconnected via a configurable interconnect system, the array comprising;

a plurality of programmable gate array (PGA) elements;

a plurality of dedicated multi-bit ALU elements each having at least one multi-bit adder and one multi-bit multiplier and being configurable in function; and

a plurality of multi-bit configurable RAM elements; and

at least one configurable multi-bit IO function unit communicatively coupled to the array;

wherein;

the interconnect system includes short segments and long segments;

one of the long segments runs parallel to a plurality of sequential short segments; and

a first of the configurable elements is connectable to a second of the configurable elements;

directly via the one of the long segments; and

indirectly, passing through one or more intermediate ones of the configurable elements arranged between the first and second configurable elements, via the plurality of sequential short segments.

43. The configurable computing processor chip of claim 42, wherein the one of the long segments includes at least one switch for passing data to at least one of the plurality of sequential short segments.

45. A configurable computing processor chip comprising:

configurable elements arranged in an array;

at least one configurable multi-bit IO function unit communicatively coupled to the array; and

a configurable interconnect system interconnecting the configurable elements;

wherein;

at least some of the configurable elements are organized in rows within the array, each of the configurable elements inside a row comprising at least one connect into the configurable interconnect system;

the array includes a plurality of programmable gate array (PGA) elements, at least one row that consists of ALU elements and at least two rows of RAM elements; and

the RAM elements receive data and address information from the configurable interconnect system and send output data directly to the configurable interconnect system.

46. The configurable computing processor chip according to claim 45, wherein the interconnect system is a segmented operand data interconnect system.

47. The configurable computing processor chip according to claim 46, wherein the interconnect system comprises short segments and long segments crossing multiple short segments.

48. The configurable computing processor chip according to claim 45, wherein the at least one IO function unit interfaces to at least one of a memory and a peripheral.

49. The configurable computing processor chip according to claim 48, wherein at least one of the at least one IO function unit comprises at least a multi-bit write data input and a multi-bit read data output.

52. The configurable computing processor chip according to claim 45, wherein the at least one configurable multi-bit IO function unit is configurable in at least one of function and interconnection.

79. The configurable computing processor chip according to claim 45, wherein the IO function unit is connected to the configurable interconnect system.

80. The configurable computing processor chip according to claim 45, wherein the IO function unit is connected directly to the configurable interconnect system.

50. A configurable computing processor chip comprising:

configurable elements arranged in an array;

at least one configurable multi-bit IO function unit communicatively coupled to the array; and

a configurable interconnect system interconnecting the configurable elements;

wherein;

at least some of the configurable elements are organized in rows within the array, each of the configurable elements inside a row comprising at least one connect into the configurable interconnect system;

the array includes a plurality of programmable gate array (PGA) elements, at least one row that consists of ALU elements and at least two rows of RAM elements; and

each of at least one of the ALU elements is at least 32-bit wide.

51. A configurable computing processor chip comprising:

configurable elements arranged in an array;

at least one configurable multi-bit IO function unit communicatively coupled to the array; and

a configurable interconnect system interconnecting the configurable elements;

wherein;

at least some of the configurable elements are organized in rows within the array, each of the configurable elements inside a row comprising at least one connect into the configurable interconnect system;

the array includes a plurality of programmable gate array (PGA) elements, at least one row that consists of ALU elements and at least two rows of RAM elements; and

an ALU of each of at least one of the plurality of ALU elements has at least 3 data inputs.

56. A configurable computing processor chip comprising:

configurable elements arranged in an array;

a configurable interconnect system interconnecting the configurable elements; and

at least one IO function unit for interfacing to at least one of a memory that is external to the processor chip and a peripheral device;

wherein;

at least some of the configurable elements are organized in rows within the array, each of the configurable elements inside a row comprising at least one connect into the configurable interconnect system;

the array includes a plurality of gate array (PGA) elements, at least one row of ALU elements and at least two rows of RAM elements;

at least one of the at least one IO function unit comprises at least a multi-bit write data input and a multi-bit read data output;

at least one of the at least one IO function unit comprises an arrangement for synchronizing a data transfer; and

each of at least one of the ALU elements is at least 32-bit wide.

59. A configurable computing processor chip comprising:

configurable elements arranged in an array;

at least one configurable multi-bit IO function unit communicatively coupled to the array; and

a configurable interconnect system interconnecting the configurable elements;

wherein;

at least some of the configurable elements are organized in rows within the array, each of the configurable elements inside a row comprising at least one connect into the configurable interconnect system;

the array includes a plurality of programmable gate array (PGA) elements, at least one row of ALU elements and at least two rows of RAM elements; and

each of at least one of the ALU elements is at least 32-bit wide.

64. A configurable computing processor chip comprising:

configurable elements for configurably processing data, the configurable elements being arranged in an array and being interconnected via a configurable interconnect system, the array comprising;

a plurality of programmable gate array (PGA) elements;

a plurality of dedicated multi-bit ALU elements each having at least one multi-bit adder and one multi-bit multiplier and being configurable in function; and

a plurality of multi-bit configurable RAM elements; and

at least one configurable multi-bit IO function unit communicatively coupled to the array;

wherein;

the at least one configurable multi-bit IO function unit is adapted for allowing interfacing to at least one of a memory and a peripheral;

at least one of the at least one IO function unit comprises at least a multi-bit write data input and a multi-bit read data output;

at least one of the at least one IO function unit comprises an arrangement for synchronizing a data transfer; and

each of at least one of the ALU elements is at least 32-bit wide.

67. A configurable computing processor chip comprising:

configurable elements for configurably processing data, the configurable elements being arranged in an array and being interconnected via a configurable interconnect system, the array comprising;

a plurality of programmable gate array (PGA) elements;

a plurality of dedicated multi-bit ALU elements each having at least one multi-bit adder and one multi-bit multiplier and being configurable in function; and

a plurality of multi-bit configurable RAM elements; and

at least one configurable multi-bit IO function unit communicatively coupled to the array;

wherein each of at least one of the ALU elements is at least 32-bit wide.

71. A configurable computing processor chip comprising:

configurable elements for configurably processing data, the configurable elements being arranged in an array and being interconnected via a configurable interconnect system, the array comprising;

a plurality of programmable gate array (PGA) elements;

a plurality of dedicated multi-bit ALU elements each having at least one multi-bit adder and one multi-bit multiplier and being configurable in function; and

a plurality of multi-bit configurable RAM elements; and

at least one configurable multi-bit IO function unit communicatively coupled to the array;

wherein;

at least some of the plurality of PGA elements are surrounded by the plurality of multi-bit ALU elements;

the configurable elements are arranged in columns and rows; and

the plurality of multi-bit configurable RAM elements are arranged at edges of the rows.

72. The configurable computing processor chip according to claim 71, further comprising:

a configuration manager that controls configuration of the configurable elements, wherein the configuration manager spans a plurality of the columns.