Switch with improved biasing

• US 8,058,922 B2
• Filed: 11/20/2009
• Issued: 11/15/2011
• Est. Priority Date: 07/28/2009
• Status: Active Grant

• Current Assignee: Qualcomm, Inc.
• Original Assignee: Qualcomm, Inc.
• Inventors: Cassia, Marco
• Primary Examiner(s): Wells, Kenneth B.
• Application Number:
  US12/623,197
• Publication Number:
  US 20110025403A1
• Time in Patent Office: 725 Days
• Field of Search: 327/308, 327/534, 327/382, 333/103
• US Class Current: 327/534
• CPC Class Codes: H03F 3/72 Gated amplifiers, i.e. amplifiers which are rendered operative or inoperative by means of a control signal
• CPC Class Codes: H03K 17/102 in field-effect transistor switches
• CPC Class Codes: H03K 17/693 Switching arrangements with several input- or output-terminals, e.g. multiplexers, distributors logic circuits H03K19/00; code converters H03M5/00, H03M7/00
• CPC Class Codes: H03K 2217/0018 Special modifications or use of the back gate voltage of a FET

Abstract

Switches with improved biasing and having better isolation and reliability are described. In an exemplary design, a switch is implemented with a set of transistors, a set of resistors, and an additional resistor. The set of transistors is coupled in a stacked configuration, receives an input signal, and provides an output signal. The set of resistors is coupled to the gates of the set of transistors. The additional resistor is coupled to the set of resistors and receives a control signal for the set of transistors. The resistors reduce signal loss through parasitic capacitances of the transistors when they are turned on. The resistors also help split the signal swing of the input signal approximately evenly across the transistors when they are turned off, which may improve reliability of the transistors. The switch may be used in a switchplexer, a power amplifier (PA) module, etc.

Claims

1. An apparatus comprising:

a plurality of transistors coupled in a stacked configuration and to receive an input signal and provide an output signal;

a plurality of resistors coupled to gates of the plurality of transistors;

an additional resistor coupled to the plurality of resistors and to receive a control signal for the plurality of transistors;

a second plurality of resistors coupled to bulk nodes of each of the plurality of transistors; and

a second additional resistor coupled between each resistor of the second plurality of resistors and a bulk voltage.

2. The apparatus of claim 1, the plurality of transistors comprise metal oxide semiconductor (MOS) transistors.

3. The apparatus of claim 1, the plurality of transistors comprise N-channel metal oxide semiconductor (NMOS) transistors.

4. The apparatus of claim 1, the plurality of resistors have equal resistor value.

5. The apparatus of claim 1, the plurality of resistors and the additional resistor have equal resistor value.

6. The apparatus of claim 1, the plurality of resistors each has a first resistor value, and the additional resistor has a second resistor value different from the first resistor value.

7. The apparatus of claim 1, the plurality of resistors and the additional resistor each has a value of at least one kilo Ohm.

8. The apparatus of claim 1, the bulk voltage is alternating current (AC) ground or a bias voltage lower than a direct current (DC) voltage of the input signal.

9. The apparatus of claim 1, the input signal comprises an input radio frequency (RF) signal, and the output signal comprises an output RF signal.

10. The apparatus of claim 9, further comprising:

a power amplifier to provide an amplified RF signal, and the input RF signal is derived based on the amplified RF signal.

11. The apparatus of claim 1, the input signal has a larger signal swing than a breakdown voltage of each transistor.

12. An integrated circuit comprising:

a plurality of metal oxide semiconductor (MOS) transistors coupled in a stacked configuration and to receive an input radio frequency (RF) signal and provide an output RF signal;

a plurality of resistors coupled to gates of the plurality of MOS transistors;

an additional resistor coupled to the plurality of resistors and to receive a control signal for the plurality of MOS transistors;

a second plurality of resistors coupled to bulk nodes of each of the plurality of MOS transistors; and

a second additional resistor coupled between each resistor of the second plurality of resistors and a bulk voltage.

13. An apparatus comprising:

a module comprising multiple switches to implement multiple signal paths, the module receives a radio frequency (RF) signal and routes the RF signal via one of the multiple signal paths, each of the multiple switches comprising

a plurality of transistors coupled in a stacked configuration,

a plurality of resistors coupled to gates of the plurality of transistors,

an additional resistor coupled to the plurality of resistors and to receive a control signal for the plurality of transistors;

a second plurality of resistors coupled to bulk nodes of each of the plurality of transistors; and

a second additional resistor coupled between each resistor of the second plurality of resistors and a bulk voltage.

14. The apparatus of claim 13, the module is a switchplexer coupled to an antenna.

15. The apparatus of claim 13, the module is a power amplifier (PA) module further comprising at least one power amplifier to amplify the RF signal.

16. The apparatus of claim 13, the apparatus is a wireless communication device.

17. A method of performing signal switching, comprising:

applying a control signal via a first resistor and further via a plurality of resistors to gates of a plurality of transistors coupled in a stacked configuration;

passing an input signal through the plurality of transistors when turned on by the control signal;

blocking the input signal from passing through the plurality of transistors when turned off by the control signal; and

biasing a bulk node of each transistor of the plurality of transistors with a bulk voltage via a second additional resistor coupled to the bulk voltage and further via a second plurality of additional resistors, each additional resistor of the second plurality of additional resistors coupled between the second additional resistor and a bulk node of a transistor of the plurality of transistors.

18. The method of claim 17, further comprising:

reducing signal loss through parasitic capacitances of the plurality of transistors with the first resistor when the plurality of transistors are turned on.

19. The method of claim 17, further comprising:

splitting signal swing of the input signal evenly across the plurality of transistors when turned off.

20. An apparatus comprising:

means for passing an input signal when turned on by a control signal and for blocking the input signal when turned off by the control signal;

means for applying the control signal via a first resistor and further via a plurality of resistors to the means for passing and blocking the input signal; and

means for biasing the means for passing and blocking the input signal with a voltage via a second resistor coupled to the voltage and further via a second plurality of additional resistors, each additional resistor of the second plurality of additional resistors coupled between the second additional resistor and the means for passing and blocking the input signal.