Chip scale power converter package having an inductor substrate

• US 8,058,960 B2
• Filed: 03/27/2007
• Issued: 11/15/2011
• Est. Priority Date: 03/27/2007
• Status: Active Grant

• Current Assignee: Alpha & Omega Semiconductor, Ltd.
• Original Assignee: Alpha & Omega Semiconductor, Ltd.
• Inventors: Sun, Ming, Hébert, François
• Primary Examiner(s): Donovan; Lincoln
• Assistant Examiner(s): CHAN, TSZFUNG JACKIE
• Application Number:
  US11/729,311
• Publication Number:
  US 20080238599A1
• Time in Patent Office: 1,694 Days
• Field of Search: 336/200, 336/232, 361/760, 296/021
• US Class Current: 336/200
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/16 of an individual bump connector
• CPC Class Codes: H01L 2224/16265 the item being a discrete passive component
• CPC Class Codes: H01L 23/5227 Inductive arrangements or effects of, or between, wiring layers other inductive arrangements H01L23/645
• CPC Class Codes: H01L 23/645 Inductive arrangements H01L23/647, H01L23/66 take precedence
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00011 Not relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01019 Potassium [K]
• CPC Class Codes: H01L 2924/0102 Calcium [Ca]
• CPC Class Codes: H01L 2924/01057 Lanthanum [La]
• CPC Class Codes: H01L 2924/01078 Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 Gold [Au]
• CPC Class Codes: H01L 2924/04941 TiN
• CPC Class Codes: H01L 2924/13091 Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
• CPC Class Codes: H01L 2924/1461 MEMS
• CPC Class Codes: H01L 2924/1902 including thick film passive components
• CPC Class Codes: H01L 2924/3025 Electromagnetic shielding
• CPC Class Codes: Y10T 29/4902 Electromagnet, transformer or inductor
• CPC Class Codes: Y10T 29/49075 including permanent magnet or core

Abstract

A chip scale power converter package having an inductor substrate and a power integrated circuit flipped onto the inductor substrate is disclosed. The inductor substrate includes a high resistivity substrate having a planar spiral inductor formed thereon.

Claims

1. A power converter package comprising:

an inductor substrate having an electrically conductive path formed from a plurality of line segments disposed on a surface, defining a spirangle inductor, the spirangle inductor comprising the plurality of line segments being straight line segments, the plurality of straight line segments maximizing an inductance of the spirangle inductor, the spirangle inductor being a predetermined angled spirangle originating at a first end and making a number of turns to a second end, wherein the plurality of straight line segments occupy substantially the same plane; and

a power integrated circuit bonded onto the spiranqle inductor substrate and in superimposition with a region of said surface, with a subset of said plurality of line segments lying outside of said region, and a plurality of contacts on said surface being outside of the spirangle inductor being connected respectively to a plurality of contacts on said surface being connected to the power integrated circuit and enclosed by the spirangle inductor by a cross over metal layer without connecting to an end of the spirangle inductor.

2. The power converter according to claim 1, wherein said power integrated circuit is bonded to said region.

3. The power converter according to claim 1, wherein the conductive path has a thickness greater than 17 microns.

4. The power converter according to claim 1, further comprising a magnetic core layer in superimposition with said spirangle inductor.

5. The power converter according to claim 4, wherein said magnetic core layer is disposed between said spirangle inductor and said power integrated circuit.

6. The power converter according to claim 2, further comprising first and second magnetic core layers coupled by means of a magnetic core material via, with said spirangle inductor being positioned between said first and second magnetic core layers.

7. The power converter according to claim 2, wherein the power integrated circuit comprises a plurality of contacts coupled to a plurality of peripheral contacts on the inductor substrate by means of a cross over metal layer.

8. The power converter according to claim 2, wherein the power integrated circuit is flip chip bonded onto the inductor substrate.

9. A chip scale inductor substrate comprising:

a high resistivity substrate having a plurality of contacts disposed on a region thereof; and

a conductive path formed from a plurality of line segments surrounding said region and defining a spirangle inductor on a surface of the substrate, the spirangle inductor comprising the plurality of line segments being straight line segments, the plurality of straight line segments maximizing an inductance of the spirangle inductor, the spirangle inductor being a predetermined angled spirangle originating at a first end and making a number of turns to a second end, wherein the plurality of straight line segments occupy substantially the same plane, with a subset of said plurality of line segments being outside said region, and a plurality of contacts on said surface being outside of the spirangle inductor being connected respectively to a plurality of contacts on said surface being connected to the power integrated circuit and enclosed by the spirangle inductor by a cross over metal layer without connecting to an end of the spirangle inductor.

10. The chip scale inductor substrate according to claim 9, wherein the conductive path has a thickness greater than 17 microns.

11. The chip scale inductor substrate according to claim 9, further comprising a plurality of magnetic core layers sandwiched by dielectric layers in superimposition with said spirangle inductor.

12. The chip scale inductor substrate according to claim 11, further comprising a magnetic core layer disposed over the spirangle inductor.

13. The chip scale inductor substrate according to claim 9, further comprising first and second magnetic core layers coupled by means of a magnetic core material via, with said spirangle inductor being positioned between said first and second magnetic core layers.

14. The chip scale inductor substrate according to claim 9, wherein the inductor substrate comprises a plurality of contacts surrounded by said plurality of line segments.

15. The chip scale inductor substrate according to claim 9, further comprising a low-K dielectric material in superimposition with said spirangle inductor to reduce parasitic capacitance.

16. A method of fabricating a chip scale power converter package comprising:

providing a substrate having a surface;

fabricating a plurality of spirangle inductors on the substrate to form a plurality of inductor substrates, with each of said spirangle inductors having a plurality of line segments, each spirangle inductor comprising the plurality of line segments being straight line segments, the plurality of straight line segments maximizing an inductance of the spirangle inductor, the spirangle inductor being a predetermined angled spirangle originating at a first end and making a number of turns to a second end, wherein the plurality of straight line segments occupy substantially the same plane;

bonding an integrated circuit onto each spirangle inductor substrate in superimposition with a region of said surface, with a subset of said plurality of line segments being outside said region, and a plurality of contacts on said surface being outside of the spirangle inductor being connected respectively to a plurality of contacts on said surface being connected to the power integrated circuit and enclosed by the spirangle inductor by a cross over metal layer without connecting to an end of the spirangle inductor; and

dicing the plurality of inductor substrates.

17. The method according to claim 16, further comprising forming a first oxide layer on the substrate before fabricating.

18. The method according to claim 17, further comprising depositing a first magnetic core material layer on the oxide layer before fabricating.

19. The method according to claim 18, further comprising depositing a second oxide layer on the magnetic core material layer before fabricating.

20. The method according to claim 19, further comprising depositing a cross over metal layer on the second oxide layer before fabricating.

21. The method according to claim 20, further comprising depositing a third oxide layer over the cross over metal layer before fabricating.

22. The method according to claim 21, further comprising depositing a dielectric material over the third oxide layer before fabricating.

23. The method according to claim 22, further comprising forming vias to the cross over metal layer before fabricating.

24. The method according to claim 23, further comprising etching exposed portions of the third oxide layer before fabricating.

25. The method according to claim 24, further comprising depositing a barrier metal layer on the dielectric material and exposed portions of the cross over metal layer before fabricating.

26. The method according to claim 25, further comprising depositing a seed layer on the barrier metal layer before fabricating.

27. The method according to claim 26, wherein the fabrication step comprises plating the plurality of spirangle inductors.

28. The method according to claim 27, wherein the fabrication step comprises patterning the plurality of spirangle inductors.

29. The method according to claim 28, further comprising etching exposed portions of the barrier metal and seed layers.

30. The method according to claim 29, further comprising depositing a first passivation layer.

31. The method according to claim 30, further comprising forming a peripheral via reaching the first magnetic core material layer.

32. The method according to claim 31, further comprising depositing a second magnetic core material layer.

33. The method according to claim 32, further comprising depositing a second passivation layer.

34. The method according to claim 33, further comprising forming contact pads in the vias.

35. The method according to claim 34, further comprising forming solder balls on the contact pads.

36. A power converter package comprising:

an inductor substrate having an electrically conductive path formed from a plurality of line segments disposed on a surface, defining a spirangle inductor, the spirangle inductor comprising the plurality of line segments being straight line segments, the plurality of straight line segments maximizing an inductance of the spirangle inductor, the spirangle inductor being a predetermined angled spirangle having at least a four angle spirangle with the spirangle inductor originating at a first end and making a number of turns to a second end in a contiguous and unitary fashion, wherein the plurality of straight line segments occupy the general same plane with the plane being generally parallel to the inductor substrate; and

a power integrated circuit bonded onto the spirangle inductor substrate, and in superimposition with a region of said surface, with a subset of said plurality of line segments lying outside of said region, and a plurality of contacts on said surface being outside of the spirangle inductor being connected respectively to a plurality of contacts on said surface being connected to the power integrated circuit and enclosed by the spirangle inductor by a cross over metal layer without connecting to an end of the spirangle inductor; and

a magnetic element associated with the spirangle inductor, the magnetic element increasing the inductance per unit area of the spirangle inductor and the magnetic element providing shielding of stray magnetic fields, wherein the power converter package is used for greater than or equal to 5 MHz frequency applications.