Content addressable memory array programmed to perform logic operations

• US 8,059,438 B2
• Filed: 08/28/2009
• Issued: 11/15/2011
• Est. Priority Date: 08/28/2009
• Status: Expired due to Fees

• Current Assignee: GlobalFoundries, Inc.
• Original Assignee: International Business Machines Corporation
• Inventors: Ji, Brian L., Ditlow, Gary S., Chang, Leland, Montoye, Robert K.
• Primary Examiner(s): Lam; David
• Application Number:
  US12/549,740
• Publication Number:
  US 20110051482A1
• Time in Patent Office: 809 Days
• Field of Search: 365/49.1, 365/163, 365/148, 365/230.06, 365/203
• US Class Current: 365/49.1
• CPC Class Codes: G11C 13/0004 comprising amorphous/crystalline phase transition cells
• CPC Class Codes: G11C 15/046 using non-volatile storage elements
• CPC Class Codes: G11C 7/1006 Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor

Abstract

A memory device for performing logical operations on two or more input variables includes a match line and first and second memory cells. The first and second memory cells collectively include a first, second, third and fourth memory element. The first, second, third and fourth memory elements may have either a first value or a second value programmed therein and wherein the first, second, third and fourth memory elements are programmed to either the high or low resistive values based on a particular logic function to be performed.

Claims

1. A memory device for performing logical operations on two or more input variables, the memory device comprising:

a match line;

a first memory cell coupled to the match line and including a first and second memory element, each memory element being coupled to a particular different logical product of a first input variable and a second input variable; and

a second memory cell coupled to the match line and including a third and fourth memory element, each memory element being coupled to a particular logical product of the first input variable and the second input variable;

wherein the first, second, third and fourth memory elements may have either a first value or a second value programmed therein and wherein the first, second, third and fourth memory elements are programmed to either the high or low resistive values based on a particular logic function to be performed.

2. The memory device of claim 1, wherein the memory device is content addressable memory and wherein the first value may be a logical 1 or a logical 0 and the second value may be a logical 1 or a logical 0.

3. The memory device of claim 1, wherein the memory device is a ternary content addressable memory and where in the first value may be a logical 1, a logical 0 or a don'"'"'t care and the second value may be a logical 1, a logical 0 or a don'"'"'t care.

4. The memory device of claim 3, wherein the first, second, third and fourth memory elements are formed of a phase change material.

5. The memory device of claim 1, further comprising:

four transistors, each transistor being coupled to a different one of the first, second, third and fourth memory elements and each having an access lines and wherein the access line of each transistor is coupled to the logical product of the first and second values.

6. The memory device of claim 5, wherein:

a first access line of a first of the four transistors is coupled to a combination of a complement of the first value and a complement of the second value;

a second access line of a second of the four transistors is coupled to a combination of the complement of the first value and the second value;

a third access line of a third of the four transistors is coupled to a combination of the first value and the complement of the second value; and

a fourth access line of a fourth of the four transistors is coupled to the first value and the second value.

7. The memory device of claim 1, further comprising:

a third memory cell coupled to the match line and including a fifth and sixth memory element, each memory element being coupled to a particular logical product of a third input variable and a fourth input variable; and

a fourth memory cell coupled to the match line and including a seventh and eighth memory element, each memory element being coupled to a particular logical product of the third input variable and the fourth input variable.

8. The memory device of claim 7, wherein the third and fourth memory cells are both activated by transistors having access lines coupled to a logical product of a third input and a fourth input.

9. A method of performing logical operations between two or more input variables, the method comprising:

providing a first two-bit cell, the first two-bit cell including a first portion and a second portion, wherein the first and second portions both include a memory cell that includes two memory elements;

coupling the first two-bit cell to a match line;

coupling a first logical product of a first input variable and a second input variable to a cell in the first portion and coupling a second logical product of the first input variable and the second input variable to a cell in the second portion, the first and second logical product being different from one another;

programming the memory elements to one of two different values based on a particular logical operation to be performed; and

monitoring a parameter of the match line to determine a result of the logical operation.

10. The method of claim 9, further comprising:

receiving an input vector at a decoder;

decoding the input vector, decoding including performing on logical operations on at least a portion of the input vector to create a plurality of selection values; and

transmitting the selection values to access lines coupled to first two-bit cell.

11. The method of claim 10, further comprising:

precharging the match line.

12. The method of claim 9, wherein programming includes matching desired logic function to a pattern of resistive values for the memory elements contained in a table.

13. The method of claim 9, further comprising:

providing a second two-bit cell, the second two-bit cell including a third portion and a fourth portion, wherein the third and fourth portion both include a memory cell that includes two memory elements;

coupling the second two-bit cell to a match line; and

programming the memory elements of the second two-bit cell to one of two different values based on a particular logical operation to be performed.

14. A memory system comprising:

a content addressable memory including a first memory cell coupled to a match line and including a first and second memory element, each memory element being coupled to a different particular logical product of the a first input variable and a second input variable, and a second memory cell coupled to the match line and including a third and fourth memory element, each memory element being coupled to a particular logical product of the first input variable and the second input variable, wherein the first, second, third and fourth memory elements may have either a first value or a second value programmed therein and wherein the first, second, third and fourth memory elements are programmed to either the high or low resistive values based on a particular logic function to be performed;

a match checking device coupled to the content addressable memory that determines if a particular input applied to the content addressable memory provides a logical 1 or logical zero as an output; and

a decoder coupled to the content addressable memory that receives an input address and decodes at least two of the bits from the address into four unique outputs.

15. The system of claim 14, wherein the first value may be a logical 1 or a logical 0 and the second value may be a logical 1 or a logical 0.

16. The system of claim 14, wherein the first value may be a logical 1, a logical 0 or a don'"'"'t care and the second value may be a logical 1, a logical 0 or a don'"'"'t care.

17. The system of claim 14, wherein the first, second, third and fourth memory elements are formed of a phase change material.