Three-dimensional memory module architectures

• US 8,059,443 B2
• Filed: 10/23/2007
• Issued: 11/15/2011
• Est. Priority Date: 10/23/2007
• Status: Active Grant

• Current Assignee: Hewlett Packard Enterprise Development LP (Hewlett-Packard Enterprise Company)
• Original Assignee: Hewlett-Packard Development Company, L.P. (HP Inc.)
• Inventors: Binkert, Nathan Lorenzo, McLaren, Moray, Jouppi, Norman Paul, Ahn, Jung Ho, Davis, Alan Lynn
• Primary Examiner(s): Nguyen; Tuan
• Assistant Examiner(s): REIDLINGER, RONALD LANCE
• Application Number:
  US11/975,963
• Publication Number:
  US 20090103345A1
• Time in Patent Office: 1,484 Days
• Field of Search: 365/64, 365/230.03, 365/51
• US Class Current: 365/64
• CPC Class Codes: G11C 13/04 using optical elements ; using other beam accessed elements, e.g. electron or ion beam
• CPC Class Codes: G11C 2211/4016 Memory devices with silicon-on-insulator cells
• CPC Class Codes: G11C 2213/71 Three dimensional array
• CPC Class Codes: G11C 5/02 Disposition of storage elements, e.g. in the form of a matrix array
• CPC Class Codes: G11C 5/025 Geometric lay-out considerations of storage- and peripheral-blocks in a semiconductor storage device geometrical lay-out of the components in integrated circuits, H01L27/0207
• CPC Class Codes: G11C 5/04 Supports for storage elements , e.g. memory modules; Mounting or fixing of storage elements on such supports
• CPC Class Codes: H01L 2225/06534 Optical coupling
• CPC Class Codes: H01L 2225/06541 Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV] manufacturing via connections per se H01L21/76898
• CPC Class Codes: H01L 2225/06565 the devices having the same size and there being no auxiliary carrier between the devices
• CPC Class Codes: H01L 25/0657 Stacked arrangements of devices
• CPC Class Codes: H01L 25/18 the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H01L 2924/15311 being a ball array, e.g. BGA

Abstract

Various embodiments of the present invention are directed to stacked memory modules. In one embodiment of the present invention, a memory module comprises at least one memory-controller layer stacked with at least one memory layer. Fine pitched through vias (e.g., through silicon vias) extend approximately perpendicular to a surface of the at least one memory controller through the stack providing electronic communication between the at least one memory controller and the at least one memory layers. Additionally, the memory-controller layer includes at least one external interface configured to transmit data to and from the memory module. Furthermore, the memory module can include an optical layer. The optical layer can be included in the stack and has a bus waveguide to transmit data to and from the at least one memory controller. The external interface can be an optical external interface which interfaces with the optical layer.

Claims

1. A memory module comprising:

a memory-controller layer including at least one memory controller;

at least one memory layer in a stack with the memory-controller layer;

an optical layer adjacent to the memory-controller layer and including a bus waveguide that lies within the optical layer, the bus waveguide having a first end to receive optical channels and a second end to send optical channels;

at least one electro-optic interface to convert optical channels input to the first end of the bus waveguide into electronic signals to be sent to the at least one memory controller and convert electronic signals received from the at least one memory controller into optical channels to be output from the second end of the bus waveguide, wherein the at least one electro-optic interface is within both the optical layer and the memory-controller layer; and

at least one set of through vias extending approximately perpendicular to a surface of the least one memory controller through the stack, each set of through vias including;

data through vias through which data is transmitted to and from the at least one memory layer;

address through vias through which a physical address of data stored in the at least one memory layer is transmitted to the at least one memory layer; and

control through vias through which commands and status signals are transmitted to and from the at least one memory layer, wherein the at least one set of at least one through vias provide electronic communication between the at least one memory controller and one of the at least one memory layers.

2. The memory module of claim 1 wherein the at least one memory layer further comprises regions, each region having at least one bank in electrical communication with the at least one memory controller via one set of the at least one set of through vias.

3. The memory module of claim 1 wherein the at least one set of through vias providing electronic communication between the at least one memory layer and the memory-controller layer further comprises the at least one set of through vias electronically coupled to at least one memory hank of the at least one memory layer and electronically coupled to the at least one memory controller of the memory-controller layer.

4. The memory module of claim 1 wherein the electro-optic interfaces further comprise:

at least one detector to convert the optical channels input to the first end of the waveguide into the electronic signals; and

at least one modulator to convert the electronic signals received from the at least one memory controller into the optical channels to be output from the second end of the bus waveguide.

5. The memory controller of claim 1 wherein the at least one set of at least one through vias further comprises approximately regularly arranged through vias with center-to-center spacing of less than approximately 50 microns.

6. The memory module of claim 1 wherein the optical layer is positioned between the memory-controller layer and the at least one memory layers and the through vias extend through the optical layer.

7. The memory module of claim 1 wherein the at least one electro-optic interface is in optical communication with the at least one bus waveguide and in electronic communication with the at least one memory controller.

8. The memory module of claim 1 wherein the optical layer further comprises an integrated mode locked laser optically coupled to the first end of the at least one bus waveguide.

9. The memory module of claim 1 wherein the at least one memory layer further comprises at least one bank disposed on a substrate and positioned adjacent to the at least one set of through vias.

10. The memory module of claim 9 wherein the at least one bank disposed on the substrate and positioned adjacent to the at least one set of through vias further comprises bit lines of the at least one bank pitch matched to the through vias.

11. The memory module of claim 9 wherein the at least one bank disposed on the substrate and positioned adjacent to the at least one set of through vias further comprises hit lines that match the bandwidth of the through vias.

12. The memory module of claim 9 wherein the at least one bank further comprises:

a number of bit lines; and

a number of sense amplifiers located near an edge of the bank adjacent to the at least one set of through vias, each sense amplifier electronically coupled to a bit line.

13. The memory modules of claim 9 wherein at least one bank further comprises a number of bit lines in electronic communication with a through via of the set of through vias.

14. The memory module of claim 13 wherein the number of bit lines in electronic communication with the through via further comprises a multiplexer electronically coupled to the number of hit lines and electronically coupled to the through via, wherein the multiplexer combines outputs from the bit lines into a single selected data output on the through via.

15. The memory module of claim 1 wherein the through vias further comprise one of:

metalized vias;

or

through silicon vias.

16. The memory module of claim 1 wherein each layer in the stack has a thickness ranging from approximately 20-50 microns.