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Semiconductor memory device with variable resistance elements

  • US 8,059,448 B2
  • Filed: 11/29/2007
  • Issued: 11/15/2011
  • Est. Priority Date: 12/08/2006
  • Status: Active Grant
First Claim
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1. A semiconductor memory device comprising:

  • a memory cell array having memory cells each composed of a variable resistance element and a switching element, the variable resistance element having a two-terminal structure and storing information when an electric resistance is changed from a first state to a second state in response to application of a first write voltage of a first polarity applied to both ends and when the electric resistance is changed from the second state to the first state in response to application of a second write voltage of a second polarity different from the first polarity applied to both ends, the switching element having one end electrically connected to one end of the variable resistance element, the memory cells being arranged in a row direction and in a column direction; and

    a writing unit configured to select one or more memory cells to be written from the memory cell array, and execute a first writing operation to change the electric resistance from the first state to the second state by applying the first write voltage to both ends of the variable resistance element of each of the selected memory cells and a second writing operation to change the electric resistance from the second state to the first state by applying the second write voltage to both ends of the variable resistance element of each of the selected memory cells,wherein the variable resistance element is configured such that (i) a same first write current flows in response to the application of the first write voltage and a same second write current flows in response to the application of the second write voltage both when the variable resistance element is in the first state and when the variable resistance element is in the second state and (ii) when a voltage of the first polarity whose absolute value is smaller than that of the first write voltage is applied, and when a voltage of the second polarity whose absolute value is smaller than that of the second write voltage is applied, a current flowing through the variable resistance element varies depending on whether the variable resistance element is in the first state or in the second state,a second memory cell number, which is a maximum number of the memory cells where the second writing operation is executed by the writing unit at the same time, is greater than a first memory cell number, which is a maximum number of the memory cells where the first writing operation is executed by the writing unit at the same time, in one part or all of the memory cells in the memory cell array,at least the second memory cell number of the first memory cell number and the second memory cell number is a plural number, andthe second memory cell number is set to be not less than a write current ratio provided by dividing the first write current by the second write current.

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