3T high density nvDRAM cell

• US 8,059,458 B2
• Filed: 12/31/2007
• Issued: 11/15/2011
• Est. Priority Date: 12/31/2007
• Status: Active Grant

• Current Assignee: Monterey Research, LLC (Vector Capital Corporation)
• Original Assignee: Cypress Semiconductor Corporation (Infineon Technologies AG)
• Inventors: Scade, Andreas, Guenther, Stefan
• Primary Examiner(s): Sofocleous, Alexander
• Application Number:
  US12/006,227
• Publication Number:
  US 20090168520A1
• Time in Patent Office: 1,415 Days
• Field of Search: 365/185.08, 365/222, 365/149, 365/185.07, 365/185.25, 365/185.28
• US Class Current: 365/185.08
• CPC Class Codes: G11C 11/405 with three charge-transfer gates, e.g. MOS transistors, per cell
• CPC Class Codes: G11C 14/0018 whereby the nonvolatile element is an EEPROM element, e.g. a floating gate or metal-nitride-oxide-silicon [MNOS] transistor

Abstract

A memory circuit includes a single transistor storing both volatile and nonvolatile bit charges.

Claims

1. A memory circuit comprising:

a single transistor storing both volatile and nonvolatile bit charges;

wherein the volatile bit charge storage is accomplished via gate-to-bulk capacitances and source-to-drain capacitances of the single transistor.

2. The memory circuit of claim 1, wherein the single transistor storing both volatile and nonvolatile bit charges further comprises:

a SONOS transistor.

3. The memory circuit of claim 1, wherein the single transistor storing both volatile and nonvolatile bit charges further comprises:

a Floating-Gate transistor.

4. The memory circuit of claim 1, further comprising:

first and second isolation transistors.

5. The memory circuit of claim 4, wherein the first and second isolation transistors further comprise:

transistors having different gate-oxide thicknesses.

6. The memory circuit of claim 1, further comprising:

a sensing circuit responsive to voltage differentials for volatile operations, and responsive to current flow for at least one nonvolatile operation.

7. The memory circuit of claim 1, further comprising:

a bit cell comprising a pair of charge cells each storing both volatile and nonvolatile bit charges.

8. The memory circuit of claim 7, wherein a single transistor of each charge cell storing both volatile and nonvolatile bit charges further comprises:

a SONOS transistor of each charge cell.

9. The memory circuit of claim 7, further comprising:

a first charge cell of the pair storing both volatile and nonvolatile bit values, and a second charge cell of the pair storing complements of the volatile and nonvolatile bit values.

10. The memory circuit of claim 9, further comprising:

the first charge cell coupled to a bit line and the second charge cell coupled to a complement bit line.

11. The memory circuit of claim 7, wherein each charge cell further comprises:

first and second isolation transistors having different gate-oxide thicknesses.

12. A method of operating a combined volatile and nonvolatile memory circuit, comprising:

causing a first charge representing a nonvolatile bit to be stored in a charge trapping region of a transistor, and causing a second charge representing a volatile bit to be stored via gate-to-bulk capacitances and source-to-drain capacitances of the transistor.

13. The method of claim 12, further comprising:

detecting the second charge as a voltage disturbance to bit line precharge levels that are approximately halfway between zero and one.

14. The method of claim 12, further comprising:

detecting the first charge via a current flow enabled when the first charge is present and absent otherwise.

15. The method of claim 12, further comprising:

refreshing the second charge from a bit line after a memory operation that affects the first charge.

16. The method of claim 15, further comprising:

refreshing the second charge from the bit line after a volatile memory READ operation that affects the first charge.

17. The method of claim 15, further comprising:

refreshing the second charge from the bit line after a nonvolatile memory ERASE operation that destroys the first charge.

18. The method of claim 15, further comprising:

refreshing the second charge from the bit line after a nonvolatile memory STORE operation that affects the first charge.

19. A device comprising:

a processor coupled to interact with a memory system, the memory system comprising;

an array of memory cells each storing a single volatile bit and a single nonvolatile bit, each cell employing a single transistor to store the volatile bit and to store the nonvolatile bit;

wherein the volatile bit charge storage is accomplished via gate-to-bulk capacitances and source-to-drain capacitances of the single transistor.

20. The device of claim 19, further comprising:

the single transistor a SONOS transistor.

21. The device of claim 19, further comprising:

each cell employing a single transistor to store a complement of the volatile bit and to store a complement of the nonvolatile bit.