Semiconductor memory having both volatile and non-volatile functionality and method of operating
First Claim
1. A semiconductor storage device comprising a plurality of memory cells connected in series and each having a floating body for storing, reading and writing data as volatile memory, and a floating gate or trapping layer for storing data as non-volatile memory, the device operating as volatile memory when power is applied to the device, and the device storing data from the volatile memory as non-volatile memory when power to the device is interrupted.
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Accused Products
Abstract
Semiconductor memory having both volatile and non-volatile modes and methods of operation. A semiconductor storage device includes a plurality of memory cells each having a floating body for storing, reading and writing data as volatile memory. The device includes a floating gate or trapping latter for storing data as non-volatile memory, the device operating as volatile memory when power is applied to the device, and the device storing data from the volatile memory, as non-volatile memory when power to the device is interrupted.
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Citations
17 Claims
- 1. A semiconductor storage device comprising a plurality of memory cells connected in series and each having a floating body for storing, reading and writing data as volatile memory, and a floating gate or trapping layer for storing data as non-volatile memory, the device operating as volatile memory when power is applied to the device, and the device storing data from the volatile memory as non-volatile memory when power to the device is interrupted.
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6. A memory string comprising a plurality of semiconductor memory cells connected in series, each said semiconductor memory cell comprising:
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a floating substrate region having a first conductivity type; first and second regions each having a second conductivity type and interfacing with the floating substrate region, such that at least a portion of the floating substrate region is located between the first and second regions and functions to store data in volatile memory; a floating gate or trapping layer positioned in between the first and second regions, adjacent a surface of the floating substrate region and insulated from the floating substrate region by an insulating layer;
the floating gate or trapping layer being configured to receive transfer of data stored by the volatile memory and store the data as nonvolatile memory in the floating gate or trapping layer upon interruption of power to the memory cell;a control gate positioned adjacent the floating gate or trapping layer; and a second insulating layer between the floating gate or trapping layer and the control gate; at least one of said floating substrate regions storing a charge or lack of charge indicative of a memory state of said respective memory cell. - View Dependent Claims (7, 8, 9, 10)
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11. A memory cell device comprising a plurality of memory strings assembled to form a grid of semiconductor memory cells, each said memory string comprising a plurality of semiconductor memory cells connected in series, each said semiconductor memory cell comprising:
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a floating substrate region having a first conductivity type; first and second regions each having a second conductivity type and interfacing with said floating substrate region, such that at least a portion of the floating substrate region is located between the first and second regions and functions to store data in volatile memory; a floating gate or trapping layer positioned in between the first and second regions, adjacent a surface of the floating substrate region and insulated from the floating substrate region by an insulating layer;
the floating gate or trapping layer being configured to receive transfer of data stored by the volatile memory and store the data as nonvolatile memory in the floating gate or trapping layer upon interruption of power to the memory cell;a control gate positioned adjacent the floating gate or trapping layer; and a second insulating layer between the floating gate or trapping layer and the control gated; at least one of said floating substrate regions storing a charge or lack of charge indicative of a memory state of said respective memory cell. - View Dependent Claims (12, 13, 14)
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15. A method of operating a semiconductor storage device, said method comprising:
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providing a semiconductor storage device having a plurality of memory cells connected in series and each having a floating body for storing, reading and writing data as volatile memory, and a floating gate or trapping layer for storing data as non-volatile memory, the device operating as volatile memory when power is applied to the device, and the device storing data from the volatile memory as non-volatile memory when power to the device is interrupted; reading and storing data to the floating bodies as volatile memory while power is applied to the device; transferring the data stored in the floating bodies, by a parallel, non-algorithmic process, to the floating gates or trapping layers corresponding to the floating bodies, when power to the device is interrupted; and storing the data in the floating gates or trapping layers as non-volatile memory.
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16. A method of operating a memory string, said method comprising:
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providing a memory string having a plurality of semiconductor memory cells connected in series, each said semiconductor memory cell comprising;
a floating substrate region having a first conductivity type;
first and second regions each having a second conductivity type and interfacing with the floating substrate region, such that at least a portion of the floating substrate region is located between the first and second regions and functions to store data in volatile memory;
a floating gate or trapping layer positioned in between the first and second regions, adjacent a surface of the floating substrate region and insulated from the floating substrate region by an insulating layer;
the floating gate or trapping layer being configured to receive transfer of data stored by the volatile memory and store the data as nonvolatile memory in the floating gate or trapping layer upon interruption of power to the memory cell;
a control gate positioned adjacent the floating gate or trapping layer; and
a second insulating layer between the floating gate or trapping layer and the control gate;reading and storing data to the floating substrate regions as volatile memory while power is applied to the device, wherein at least one of said floating substrate regions stores a charge or lack of charge indicative of a memory state of said respective memory cell; transferring the data stored in the floating substrate regions, by a parallel, non-algorithmic process, to the floating gates or trapping layers corresponding to the floating substrate regions, when power to the device is interrupted; and storing the data in the floating gates or trapping layers as non-volatile memory.
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17. A method of operating a memory cell device, said method comprising:
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providing a memory cell device comprising a plurality of memory strings assembled to form a grid of semiconductor memory cells, each said memory string comprising a plurality of semiconductor memory cells connected in series, each said semiconductor memory cell comprising;
a floating substrate region having a first conductivity type;
first and second regions each having a second conductivity type and interfacing with said floating substrate region, such that at least a portion of the floating substrate region is located between the first and second regions and functions to store data in volatile memory;
a floating gate or trapping layer positioned in between the first and second regions, adjacent a surface of the floating substrate region and insulated from the floating substrate region by an insulating layer;
the floating gate or trapping layer being configured to receive transfer of data stored by the volatile memory and store the data as nonvolatile memory in the floating gate or trapping layer upon interruption of power to the memory cell;
a control gate positioned adjacent the floating gate or trapping layer; and
a second insulating layer between the floating gate or trapping layer and the control gate;reading and storing data to the floating substrate regions as volatile memory while power is applied to the device, wherein at least one of said floating substrate regions stores a charge or lack of charge indicative of a memory state of said respective memory cell; transferring the data stored in the floating substrate regions, by a parallel, non-algorithmic process, to the floating gates or trapping layers corresponding to the floating substrate regions, when power to the device is interrupted; and storing the data in the floating gates or trapping layers as non-volatile memory.
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Specification