Low power consumption GNSS receiver and method thereof

• US 8,059,699 B2
• Filed: 05/11/2007
• Issued: 11/15/2011
• Est. Priority Date: 05/11/2007
• Status: Expired due to Fees

• Current Assignee: MediaTek, Inc.
• Original Assignee: MediaTek, Inc.
• Inventors: You, Zong-hua, Lee, Ming-hung, Yeh, Hsin-chung
• Primary Examiner(s): ODOM, CURTIS B
• Application Number:
  US11/747,736
• Publication Number:
  US 20080279260A1
• Time in Patent Office: 1,649 Days
• Field of Search: 375/142, 375/150, 375/343, 375/134, 375/145, 375/149
• US Class Current: 375/150
• CPC Class Codes: G01S 19/34 Power consumption
• CPC Class Codes: H04W 52/029 reducing the clock frequency of the controller
• CPC Class Codes: Y02D 30/70 in wireless communication networks

Abstract

Disclosed is a low power consumption GNSS receiver by adaptively adjusting clock frequency. A correlator performs correlations to signals received from the channels with a correlator clock frequency. A DSP controls the correlator clock frequency according to a correlator load to performing correlations. The DSP calculates and adjusts code phases and Doppler frequencies for the signals in turn with a DSP clock frequency. The DSP controls the DSP clock frequency according to an accumulated throughput of calculation and adjustment or a predetermined threshold number of channels. The DSP controls the RF power according to the correlator load. A microprocessor processes a measurement result of the calculation and the adjustment for obtaining position information with a microprocessor clock frequency. The microprocessor controls the microprocessor clock frequency according to an accumulated progress of processing the measurement result. Accordingly, reducing power consumption for the GNSS receiver can be realized.

Claims

1. A low power consumption GNSS receiver receiving a plurality of signals from a plurality of channels, the GNSS receiver comprising:

a correlator, performing correlations to the signals from the channels with a correlator clock frequency; and

a DSP, controlling the correlator clock frequency according to a correlator load to perform correlations;

calculating and adjusting code phases and Doppler frequencies for the signals from the channels in turn with a DSP clock frequency;

controlling the DSP clock frequency according to an accumulated throughput of calculation and adjustment for the code phase and the Doppler frequencies;

raising the DSP clock frequency if the accumulated throughput lags behind a ratio of a predeteremined channel number to a number of total channels after calculating and adjusting for the signals from the channels of the predetermined number.

2. The GNSS receiver of claim 1, wherein the correlator load depends on the number of the channels that the correlator performs correlation to the signals therethrough.

3. The GNSS receiver of claim 1, wherein the correlator load depends on range of code-frequency domains for searching or tracking the signals.

4. The GNSS receiver of claim 1, wherein the DSP lowers the correlator clock frequency after obtaining position information.

5. The GNSS receiver of claim 1, wherein the DSP lowers the correlator clock frequency after one satellite is acquired.

6. A low power consumption GNSS receiver receiving a plurality of signals from a plurality of channels, the GNSS receiver comprising:

a correlator, performing correlations to the signals from the channels with a correlator clock frequency;

a DSP, controlling the correlator clock frequency according to a correlator load to perform correlations, and calculating and adjusting code phases and Doppler frequencies for the signals from the channels in turn with a DSP clock frequency; and

a microprocessor, processing a measurement result of the calculation and the adjustment for the code phase and the Doppler frequencies from the DSP for obtaining position information with a microprocessor clock frequency, controlling the microprocessor clock frequency according to an accumulated progress of processing the measurement result, and raising the microprocessor clock frequency if the accumulated progress lags behind a ratio of the predetermined period to a period for processing the measurement result of total channels after processing the measurement result of the predetermined period.

7. A method to achieve low power consumption for a GNSS receiver, the method comprising steps of:

performing correlations to a plurality of signals received from a plurality of channels with a correlator clock frequency;

controlling the correlator clock frequency according to a correlator load to perform correlations;

calculating and adjusting code phases and Doppler frequencies for the signals from the channels in turn with a DSP clock;

controlling the DSP clock frequency according to an accumulated throughput of calculation and adjustment for the code phase and the Doppler frequencies during the step of calculating and adjusting code phase and Doppler frequencies; and

raising the DSP clock frequency if the accumulated throughput lags behind a ratio of a predetermined channel number to a number of total channels after calculating and adjusting for the signals from the channels of the predetermined number during the controlling step.

8. The method of claim 7, further comprising a step of lowering the correlator clock frequency after obtaining position information.

9. The method of claim 7, further comprising a step of lowering the correlator clock frequency after one satellite is acquired during the controlling step.

10. A method to achieve low power consumption for a GNSS receiver, the method comprising steps of:

performing correlation to a correlator to perform correlations;

controlling the correlator frequency according to a correlator load to perform correlations;

calculating and adjusting code phases and Doppler frequencies for the signals from the channels in turn with a DSP clock frequency;

processing a measurement result of the calculation and the adjustment for the code phases and the Doppler frequencies from the DSP for obtaining position information with a microprocessor clock frequency after the step of calculating and adjusting code phases and Doppler frequencies;

controlling the microprocessor clock frequency according to an accumulated progress of processing the measurement result during the step of processing the measurement; and

raising the microprocessor clock frequency if the accumulated progress lags behind a ratio of the predetermined period to a period for processing the measurement result of total channels after processing the measurement result of the predetermined period during the controlling step.