Interface circuit and method for programming or communicating with an integrated circuit via a power supply pin

• US 8,060,661 B1
• Filed: 03/27/2007
• Issued: 11/15/2011
• Est. Priority Date: 03/27/2007
• Status: Active Grant

• Current Assignee: Monterey Research, LLC (Vector Capital Corporation)
• Original Assignee: Cypress Semiconductor Corporation (Infineon Technologies AG)
• Inventors: Wright, David G.
• Primary Examiner(s): Kindred, Alford
• Assistant Examiner(s): ABAD, FARLEY J
• Application Number:
  US11/691,676
• Time in Patent Office: 1,694 Days
• Field of Search: 710/7, 710/8, 710/104, 714/734
• US Class Current: 710/8
• CPC Class Codes: G06F 1/22 Means for limiting or controlling the pin/gate ratio

Abstract

An interface circuit and method for programming or communicating with an integrated circuit (IC) via a power supply pin is provided herein. In general, the power supply pin may be coupled for receiving a relatively constant voltage signal during a first mode of operation (i.e., a normal mode) and a modulated voltage signal during a second mode of operation (i.e., a programming or communication mode). The interface circuit may be coupled between the power supply pin and other IC components for decoding the modulated voltage signal into data. Various encoding/decoding schemes may be used by the interface circuit and method for communicating data to the IC over the power supply lines. The decoded data may be used for programming or communication purposes.

Claims

1. A method for programming an integrated circuit through a power supply pin configured to supply power to integrated circuit components, the method comprising:

generating a power-on reset event by applying power to the power supply pin;

generating a first modulation sequence on the power supply pin, wherein the first modulation sequence provides instructions for entering a programming mode of operation;

receiving a second modulation sequence on the power supply pin, wherein the second modulation sequence confirms entering the programming mode of operation and is generated by an internal integrated circuit component;

generating a third modulation sequence on the power supply pin, wherein the third modulation sequence provides programming instructions for programming a non-volatile memory; and

receiving a fourth modulation sequence, wherein the fourth modulation sequence confirms receipt of the programming instructions and is generated by an internal integrated component.

2. The method of claim 1, further comprising terminating the programming mode.

3. The method of claim 1, further comprising:

generating a fifth modulation sequence on the power supply pin, wherein the fifth modulation provides instructions for entering a non-programming mode; and

receiving a sixth modulation sequence on the power supply pin, wherein the sixth modulation sequence confirms entering the non-programming mode.

4. The method of claim 1, wherein the programming instructions comprise instructions for erasing one or more non-volatile memory elements.

5. A programming device configured to provide programming instructions to an integrated circuit through a power supply pin, the power supply in configured to supply power to integrated circuit components, the programming device configured to:

trigger a power-on-reset (POR) event on the integrated circuit;

provide a first voltage signal on the power supply pin to cause the integrated circuit to enter a programming mode of operation;

receive a second voltage signal on the power supply pin to confirm entry into the programming mode by the integrated circuit, the second voltage signal being generated by an internal integrated circuit component;

provide a third voltage signal on the power supply pin to provide programming instructions for programming a non-volatile memory; and

receive a fourth voltage signal on the power supply pin to confirm receipt of the programming instructions, the fourth voltage signal being generated by an internal integrated circuit component.

6. The programming device of claim 5 further configured to terminate programming mode.

7. The programming device of claim 5, further configured to generate a fifth voltage signal on the power supply pin to cause the integrated circuit to enter a non-programming mode and to receive a sixth voltage signal on the power supply pin to confirm entry into a non-programming mode by the integrated circuit.

8. The programming device of claim 5 wherein the programming instructions comprise instructions for erasing one or more non-volatile memory elements.

9. The programming device of claim 5 wherein the voltage signals are generated by toggling a programming output between a first voltage and a second voltage.

10. The system of claim 9 wherein the programming instructions comprise instructions to erase one or more non-volatile memory elements.

11. A system comprising:

a programmer configured to send programming instructions; and

an integrated circuit configured to receive programming instructions from the programmer on a power supply pin, the power supply pin configured to supply power to integrated circuit components;

wherein the programmer is configured to trigger a power-on-reset event on the integrated circuit and to provide a first plurality of modulation signals to the integrated circuit for entry into a programming mode of operation and to send programming instructions, and

wherein the integrated circuit is configured to detect each of the first plurality of modulation signals and to send a second plurality of modulation signals to confirm entry into a programming mode of operation and receipt of programming instructions, the second plurality of modulation signals being generated by an internal integrated circuit component; and

wherein the integrated circuit is configured to program a non-volatile memory according to the programming instructions.