Integrated circuit having a plurality of interfaces and integrated circuit card having the same

• US 8,060,664 B2
• Filed: 01/19/2007
• Issued: 11/15/2011
• Est. Priority Date: 05/18/2006
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Chung, Hwi-Taek, Kim, Ki-Hong
• Primary Examiner(s): Dang; Khanh
• Application Number:
  US11/655,328
• Publication Number:
  US 20080010562A1
• Time in Patent Office: 1,761 Days
• Field of Search: 710/10, 710/11, 710 14- 19, 710/300, 710/301, 710/305, 710/306, 710/313
• US Class Current: 710/11
• CPC Class Codes: G06F 13/4291 using a clocked protocol
• CPC Class Codes: G06K 19/0723 the record carrier comprising an arrangement for non-contact communication, e.g. wireless communication circuits on transponder cards, non-contact smart cards or RFIDs

Abstract

An integrated circuit supporting a first interface and a second interface and an integrated circuit card having the same includes the first interface capable of communicating with a first host, the second interface communicating with a second host, and a control block. The control block activates the second interface when a voltage level of a contact that the second host can be connected is in a first state at a first-occurring timepoint between a reference timepoint and a state transition timepoint of an external reset signal output from the first host, and deactivates the second interface when the voltage level of the contact is in a second state. The integrated circuit card has the integrated circuit built in.

Claims

1. An integrated circuit comprising:

a plurality of eight electrical contacts conforming to ISO 7816 standards;

a first interface capable of communicating with a first host by utilizing no more than seven of the eight electrical contacts, using one or more ISO 7816 standard protocols;

a second interface capable of communicating with a second host by utilizing only one of the eight electrical contacts, said second interface not utilizing any of the electrical contacts utilized by the first interface, wherein the second interface communicates with the second host using a single wire protocol (SWP); and

a control block determining a voltage level of a contact connected to the second host at a first-occurring timepoint between a reference timepoint and a state transition timepoint of an external reset signal output from the first host.

2. The integrated circuit of claim 1, wherein the control block comprises:

a CPU;

an internal clock signal generator generating an internal clock signal in response to a start signal;

a detection circuit generating a first reset signal and a mode signal based on the start signal, the internal clock signal, the external reset signal, and the voltage level of the contact;

a first selection circuit outputting either an external clock signal output from the first host or the internal clock signal to the CPU based on the mode signal;

a second selection circuit outputting either the external reset signal output from the first host or the first reset signal to the CPU based on the mode signal; and

a switch outputting the internal clock signal to the second interface selectively based on the mode signal.

3. The integrated circuit of claim 2, wherein the CPU releases a reset in response to a second reset signal output from the second selection circuit.

4. The integrated circuit of claim 2, wherein the detection circuit comprises:

a reset signal edge detector detecting a state transition edge of the external reset signal output from the first host and generating a detection signal;

a timer outputting a first indication signal indicating the reference timepoint in response to the start signal and the internal clock signal;

an edge detection timepoint determination circuit outputting a second indication signal indicating the first-occurring timepoint in response to the detection signal and the first indication signal; and

a state detection circuit determining the voltage level of the contact based on the second indication signal, and generating the first reset signal and the mode signal based on a result of the determination.

5. The integrated circuit of claim 2, wherein when the mode signal is activated based on the voltage level of the contact having a first state, the first selection circuit outputs the internal clock signal to the CPU, the second selection circuit outputs the first reset signal to the CPU, and the switch outputs the internal clock signal to the second interface, each in response to the mode signal.

6. The integrated circuit of claim 2, wherein when the mode signal is deactivated based on the voltage level of the contact having a second state, the first selection circuit outputs the external clock signal to the CPU, the second selection circuit outputs the external reset signal to the CPU, and the switch shuts off, each in response to the deactivated mode signal.

7. The integrated circuit of claim 1, wherein the plurality of eight electrical contacts include a C1 contact, a C2 contact, a C3 contact, a C4 contact, a C5 contact, a C6 contact, a C7 contact, and a C8 contact, as defined by ISO 7816 standards, and the first interface utilizes the following contacts:

C1, C2, C3, C4, C5, C7, and C8, but cannot utilize the C6 contact, and the second interface is capable of utilizing the C6 contact, but cannot utilize the following contacts;

C1, C2, C3, C4, C5, C7, and C8.

8. An integrated circuit card comprising:

a plurality of eight electrical contacts conforming to ISO 7816 standards; and

an integrated circuit connected to the plurality of contacts,

wherein the integrated circuit includes,

a first interface capable of communicating with a first host through a first contact among the plurality of contacts using a ISO 7816 protocol;

a second interface capable of communicating with a second host through a second contact among the plurality of contacts using a single wire protocol (SWP); and

a control block determining a voltage level of the second contact at a first-occurring timepoint between a reference timepoint and a state transition timepoint of an external reset signal output from the first host, and deactivating the second interface selectively-based on a result of the determination,

wherein the first interface is not capable of utilizing the second contact and the second interface is not capable of utilizing the first contact.

9. The integrated circuit of claim 8, wherein the control block comprises:

a CPU;

an internal clock signal generator generating an internal clock signal in response to a start signal;

a detection circuit generating a first reset signal and a mode signal based on the start signal, the internal clock signal, the external reset signal, and the voltage level of the second contact;

a first selection circuit outputting either an external clock signal output from the first host or the internal clock signal to the CPU based on the mode signal

a second selection circuit outputting either the external reset signal output from the first host or the first reset signal to the CPU based on the mode signal; and

a switch outputting the internal clock signal to the second interface selectively based on the mode signal.

10. The integrated circuit of claim 9, wherein the CPU releases a reset in response to a second reset signal output from the second selection circuit.

11. The integrated circuit of claim 9, wherein the detection circuit comprises:

a reset signal edge detector detecting a state transition edge of the external reset signal output from the first host and generating a detection signal;

a timer outputting a first indication signal indicating the reference timepoint in response to the start signal and the internal clock signal;

an edge detection timepoint determination circuit outputting a second indication signal indicating the first-occurring timepoint in response to the detection signal and the first indication signal; and

a state detection circuit determining the voltage level of the second contact based on the second indication signal, and generating the first reset signal and the mode signal based on a result of the determination.

12. The integrated circuit of claim 9, wherein when the mode signal is activated based on the voltage level of the second contact having a first state, the first selection circuit outputs the internal clock signal to the CPU, the second selection circuit outputs the first reset signal to the CPU, and the switch outputs the internal clock signal to the second interface, each in response to the mode signal.

13. The integrated circuit of claim 9, wherein when the mode signal is inactivated based on the voltage level of the contact in a second state, the first selection circuit outputs the external clock signal to the CPU, the second selection circuit outputs the external reset signal to the CPU, and the switch becomes off, each in response to the deactivated mode signal.

14. An integrated circuit comprising:

a plurality of eight electrical contacts conforming to ISO 7816 standards;

a first interface capable of communicating with a first host by utilizing no more than seven of the eight electrical contacts, using one or more ISO 7816 standard protocols;

a second interface capable of communicating with a second host by utilizing only one of the eight electrical contacts and radio frequency (RF) communication, said second interface not utilizing any of the electrical contacts utilized by the first interface; and

a control block determining a voltage level of a contact connected to the second host at a first-occurring timepoint between a reference timepoint and a state transition timepoint of an external reset signal output from the first host.

15. The integrated circuit of claim 14, wherein the plurality of eight electrical contacts include a C1 contact, a C2 contact, a C3 contact, a C4 contact, a C5 contact, a C6 contact, a C7 contact, and a C8 contact, as defined by ISO 7816 standards, and the first interface utilizes the following contacts:

C1, C2, C3, C4, C5, C7, and C8, but cannot utilize the C6 contact, and the second interface is capable of utilizing the C6 contact, but cannot utilize the following contacts;

C1, C2, C3, C4, C5, C7, and C8.