Multiprocessor system having an input/output (I/O) bridge circuit for transferring data between volatile and non-volatile memory

• US 8,060,708 B2
• Filed: 05/28/2010
• Issued: 11/15/2011
• Est. Priority Date: 08/18/2006
• Status: Active Grant

• Current Assignee: Cypress Semiconductor Corporation (Infineon Technologies AG)
• Original Assignee: Cypress Semiconductor Corporation (Infineon Technologies AG)
• Inventors: Maheshwari, Dinesh, Ramanathan, Dinesh, Chetia, Alakesh, Letourneur, Herve, Smith, Donald W., Gujral, Manoj
• Primary Examiner(s): Kim, Hong
• Application Number:
  US12/790,712
• Publication Number:
  US 20100312952A1
• Time in Patent Office: 536 Days
• Field of Search: 711/154, 711/102, 711/104, 711/5, 711/103, 711/105, 711/157, 703/13, 703/23
• US Class Current: 711/154
• CPC Class Codes: G06F 12/0638 Combination of memories, e.g. ROM and RAM such as to permit replacement or supplementing of words in one module by words in another module address formation of the next microinstruction G06F9/26; masking faults in memories by using spares or by reconfiguring G11C29/70
• CPC Class Codes: G06F 13/1694 Configuration of memory controller to different memory types

Abstract

A disclosed circuit includes circuitry for coupling to a volatile memory, circuitry for coupling to a nonvolatile NAND flash memory, and circuitry that: (i) receives a volatile memory request from a processor and satisfies the volatile memory request by accessing the volatile memory, and (ii) receives a nonvolatile NOR flash memory read request from the processor and satisfies the NOR read request by accessing both the NAND flash memory and the volatile memory. The circuit may also include circuitry that receives a volatile memory request from another processor and satisfies the volatile memory request from the other processor by accessing the volatile memory, and circuitry that receives a NAND flash memory read request from the other processor and satisfies the NAND read request by accessing the NAND flash memory. Multiprocessor systems including the circuit are described, as is a method for satisfying a NOR flash memory read request.

Claims

1. A method comprising:

receiving, at a first interface of a circuit, a first volatile memory read request from a first processor coupled with the circuit and satisfying the first volatile memory read request through accessing SDRAM of the circuit, the SDRAM configured to be coupled with an SDRAM controller of the circuit;

receiving, at the first interface, a first nonvolatile memory read request from the first processor and satisfying the first nonvolatile read request through accessing the SDRAM and NAND flash memory of the circuit, the NAND flash memory configured to be coupled with a NAND flash memory controller of the circuit;

receiving, at a second interface of the circuit, a second volatile memory read request from a second processor coupled with the circuit and satisfying the second volatile memory read request through accessing the SDRAM;

receiving, at a third interface of the circuit, a second nonvolatile memory read request from the second processor and satisfying the second nonvolatile memory read request through accessing the NAND flash memory; and

carrying out interprocessor communication between the first processor and the second processor utilizing a dual port random access memory (RAM) of the circuit, the dual port RAM comprising an addressable memory location accessible to the first processor and the second processor, the first nonvolatile memory read request comprising NOR flash memory access signals, and the first volatile memory read request comprising static random access memory (SRAM) access signals.

2. A method comprising:

receiving a first volatile memory read request from a first processor and accessing a volatile memory responsive to the first volatile memory read request;

receiving a first nonvolatile memory read request from the first processor and accessing the volatile memory and a non-volatile memory responsive to the first nonvolatile read request;

receiving a second volatile memory read request from a second processor and accessing the volatile memory responsive to the second volatile memory read request;

receiving a second nonvolatile memory read request from the second processor and accessing the non-volatile memory responsive to the second nonvolatile memory read request; and

scheduling an order of accessing the volatile memory or the nonvolatile memory responsive to at least one of the first volatile memory read request, the first nonvolatile memory read request, the second volatile memory read request, and the second nonvolatile memory read request to meet latency and timing requirements.

3. The method of claim 2, wherein the receiving of the first volatile memory read request from the first processor includes receiving static random access memory (SRAM) access signals, and the accessing of the volatile memory responsive to the first volatile memory read request includes accessing a synchronous dynamic random access memory (SDRAM).

4. The method of claim 2, wherein the receiving of the first nonvolatile memory read request from the first processor includes receiving NOR flash memory access signals, and the accessing of the nonvolatile memory responsive to the first nonvolatile memory read request includes accessing a NAND flash memory.

5. The method of claim 2, wherein the receiving of the second volatile memory read request from the second processor includes receiving synchronous dynamic random access memory (SDRAM) access signals, and the accessing of the volatile memory responsive to the second volatile memory read request includes accessing the SDRAM.

6. The method of claim 2, wherein the receiving of the second nonvolatile memory read request from the second processor includes receiving NAND flash memory access signals, and accessing of the nonvolatile memory responsive to the second nonvolatile memory read request includes accessing the NAND flash memory.

7. The method of claim 2, wherein the accessing of the volatile memory and the nonvolatile memory responsive to the first nonvolatile read request includes transferring requested data from the nonvolatile memory to the volatile memory using a direct memory access (DMA) operation.

8. The method of claim 2, wherein the scheduling the order of accessing the nonvolatile memory includes scheduling the order responsive to priority information associated with NOR flash memory access signals and NAND flash memory signals, and the accessing of the nonvolatile memory includes accessing a NAND flash memory in the scheduled order.

9. The method of claim 2, wherein the accessing of the nonvolatile memory includes accessing a NAND flash memory through a universal serial bus.

10. A memory interface comprising:

a transaction interleaver coupled with a first processor through a first interface and a second processor through a second interface and a third interface, the transaction interleaver further coupled to a volatile memory and a nonvolatile memory, the transaction interleaver configured to;

receive a first volatile memory read request from the first processor through the first interface and satisfy the first volatile memory read request through the volatile memory;

receive a first nonvolatile memory read request from the first processor through the first interface and satisfy the first nonvolatile read request through the volatile memory and the nonvolatile memory;

receive a second volatile memory read request from the second processor through the second interface and satisfy the second volatile memory read request through the volatile memory;

receive a second nonvolatile memory read request from the second processor through the third interface and satisfy the second nonvolatile memory read request through accessing the nonvolatile memory; and

schedule an order of satisfaction of at least one of the first volatile memory read request, the first nonvolatile memory read request, the second volatile memory read request, and the second nonvolatile memory read request in an order that meets latency and timing requirements.

11. The memory interface of claim 10, wherein the first volatile memory read request comprises static random access memory (SRAM) access signals and the volatile memory comprises synchronous dynamic random access memory (SDRAM).

12. The memory interface of claim 10, wherein the first nonvolatile memory read request comprises NOR flash memory access signals and the nonvolatile memory comprises NAND flash memory.

13. The memory interface of claim 10, wherein the second volatile memory read request comprises synchronous dynamic random access memory (SDRAM) access signals the volatile memory comprises SDRAM.

14. The memory interface of claim 10, wherein the second nonvolatile memory read request comprises NAND flash memory access signals and the nonvolatile memory comprises NAND flash memory.

15. The memory interface as recited in claim 14, wherein the second nonvolatile memory read request comprises NAND memory access signals forwarded from the second processor to the memory interface.

16. The memory interface of claim 10, further comprising a direct memory access controller (DMA), wherein the satisfaction of the first nonvolatile read request through the volatile memory and the nonvolatile memory includes the DMA controller configured to transfer requested data from the nonvolatile memory to the volatile memory through a DMA operation, wherein the transaction interleaver is configured to access the transferred requested data in the volatile memory.

17. The memory interface of claim 10, wherein the first nonvolatile memory read request includes NOR flash memory access signals, the second nonvolatile memory read request includes NAND flash memory access signals, and the nonvolatile memory includes NAND flash memory, wherein the transaction interleaver is configured to schedule the order of satisfaction of the first nonvolatile memory read request and the second nonvolatile memory read request based on priority information associated with at least one of the NOR flash memory access signals and the NAND flash memory access signals.

18. The memory interface as recited in claim 10, further comprising a configuration register containing priority information, which is used by the transaction interleaver to schedule the order in which the first and second nonvolatile memory read requests are satisfied.

19. The memory interface as recited in claim 10, further comprising a dual port RAM configured to facilitate a grant of access to the first processor or the second processor via data stored in at least one memory location of the dual port RAM.

20. The memory interface of claim 10, further comprising a universal serial bus (USB) interface, wherein the nonvolatile memory comprises NAND flash memory that is accessible through the USB interface.