Multiprocessor system having an input/output (I/O) bridge circuit for transferring data between volatile and non-volatile memory
First Claim
1. A method comprising:
- receiving, at a first interface of a circuit, a first volatile memory read request from a first processor coupled with the circuit and satisfying the first volatile memory read request through accessing SDRAM of the circuit, the SDRAM configured to be coupled with an SDRAM controller of the circuit;
receiving, at the first interface, a first nonvolatile memory read request from the first processor and satisfying the first nonvolatile read request through accessing the SDRAM and NAND flash memory of the circuit, the NAND flash memory configured to be coupled with a NAND flash memory controller of the circuit;
receiving, at a second interface of the circuit, a second volatile memory read request from a second processor coupled with the circuit and satisfying the second volatile memory read request through accessing the SDRAM;
receiving, at a third interface of the circuit, a second nonvolatile memory read request from the second processor and satisfying the second nonvolatile memory read request through accessing the NAND flash memory; and
carrying out interprocessor communication between the first processor and the second processor utilizing a dual port random access memory (RAM) of the circuit, the dual port RAM comprising an addressable memory location accessible to the first processor and the second processor, the first nonvolatile memory read request comprising NOR flash memory access signals, and the first volatile memory read request comprising static random access memory (SRAM) access signals.
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Accused Products
Abstract
A disclosed circuit includes circuitry for coupling to a volatile memory, circuitry for coupling to a nonvolatile NAND flash memory, and circuitry that: (i) receives a volatile memory request from a processor and satisfies the volatile memory request by accessing the volatile memory, and (ii) receives a nonvolatile NOR flash memory read request from the processor and satisfies the NOR read request by accessing both the NAND flash memory and the volatile memory. The circuit may also include circuitry that receives a volatile memory request from another processor and satisfies the volatile memory request from the other processor by accessing the volatile memory, and circuitry that receives a NAND flash memory read request from the other processor and satisfies the NAND read request by accessing the NAND flash memory. Multiprocessor systems including the circuit are described, as is a method for satisfying a NOR flash memory read request.
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Citations
20 Claims
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1. A method comprising:
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receiving, at a first interface of a circuit, a first volatile memory read request from a first processor coupled with the circuit and satisfying the first volatile memory read request through accessing SDRAM of the circuit, the SDRAM configured to be coupled with an SDRAM controller of the circuit; receiving, at the first interface, a first nonvolatile memory read request from the first processor and satisfying the first nonvolatile read request through accessing the SDRAM and NAND flash memory of the circuit, the NAND flash memory configured to be coupled with a NAND flash memory controller of the circuit; receiving, at a second interface of the circuit, a second volatile memory read request from a second processor coupled with the circuit and satisfying the second volatile memory read request through accessing the SDRAM; receiving, at a third interface of the circuit, a second nonvolatile memory read request from the second processor and satisfying the second nonvolatile memory read request through accessing the NAND flash memory; and carrying out interprocessor communication between the first processor and the second processor utilizing a dual port random access memory (RAM) of the circuit, the dual port RAM comprising an addressable memory location accessible to the first processor and the second processor, the first nonvolatile memory read request comprising NOR flash memory access signals, and the first volatile memory read request comprising static random access memory (SRAM) access signals.
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2. A method comprising:
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receiving a first volatile memory read request from a first processor and accessing a volatile memory responsive to the first volatile memory read request; receiving a first nonvolatile memory read request from the first processor and accessing the volatile memory and a non-volatile memory responsive to the first nonvolatile read request; receiving a second volatile memory read request from a second processor and accessing the volatile memory responsive to the second volatile memory read request; receiving a second nonvolatile memory read request from the second processor and accessing the non-volatile memory responsive to the second nonvolatile memory read request; and scheduling an order of accessing the volatile memory or the nonvolatile memory responsive to at least one of the first volatile memory read request, the first nonvolatile memory read request, the second volatile memory read request, and the second nonvolatile memory read request to meet latency and timing requirements. - View Dependent Claims (3, 4, 5, 6, 7, 8, 9)
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10. A memory interface comprising:
a transaction interleaver coupled with a first processor through a first interface and a second processor through a second interface and a third interface, the transaction interleaver further coupled to a volatile memory and a nonvolatile memory, the transaction interleaver configured to; receive a first volatile memory read request from the first processor through the first interface and satisfy the first volatile memory read request through the volatile memory; receive a first nonvolatile memory read request from the first processor through the first interface and satisfy the first nonvolatile read request through the volatile memory and the nonvolatile memory; receive a second volatile memory read request from the second processor through the second interface and satisfy the second volatile memory read request through the volatile memory; receive a second nonvolatile memory read request from the second processor through the third interface and satisfy the second nonvolatile memory read request through accessing the nonvolatile memory; and schedule an order of satisfaction of at least one of the first volatile memory read request, the first nonvolatile memory read request, the second volatile memory read request, and the second nonvolatile memory read request in an order that meets latency and timing requirements. - View Dependent Claims (11, 12, 13, 14, 15, 16, 17, 18, 19, 20)
Specification