Hybrid memory management
DCFirst Claim
1. A method for managing data stored on a memory device comprising a first array of memory cells each memory cell having a first density and a second array of memory cells each memory cell having a second density, comprising:
- determining usage associated with a logical address of the memory device;
at least partially based on the usage, storing data associated with the logical address in one of the first array and second array of memory cells; and
maintaining at least a particular number of spare locations in the first array of memory cells if locations are available in the second array of memory cells by moving data from the first array of memory cells to the second array of memory cells.
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Accused Products
Abstract
Methods and apparatus for managing data storage in hybrid memory devices utilizing single level and multi level memory cells. Logical addresses can be distributed between single level and multilevel memory cells based on a frequency of write operations performed. Initial storage of data corresponding to a logical address in memory can be determined by various methods including initially writing all data to single level memory or initially writing all data to multilevel memory. Other methods permit a host to direct logical address writes to single level or multilevel memory cells based on anticipated usage.
32 Citations
36 Claims
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1. A method for managing data stored on a memory device comprising a first array of memory cells each memory cell having a first density and a second array of memory cells each memory cell having a second density, comprising:
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determining usage associated with a logical address of the memory device; at least partially based on the usage, storing data associated with the logical address in one of the first array and second array of memory cells; and maintaining at least a particular number of spare locations in the first array of memory cells if locations are available in the second array of memory cells by moving data from the first array of memory cells to the second array of memory cells. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15)
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16. A non-volatile memory device having physical storage locations associated with logical addresses, and wherein the logical addresses are associated with data, the memory device comprising:
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a first array of memory cells each memory cell having a first density; a second array of memory cells each memory cell having a second density; and a controller, wherein the controller is configured to selectively perform a write operation on the first array of memory cells or on the second array of memory cells and to assign the logical addresses to the physical storage locations based at least partially on a number of write operations performed on each logical address, and to re-assign logical addresses to the first array of memory cells if the number of write operations exceeds a threshold value and wherein the control circuitry is further configured to maintain at least a particular number of spare locations in the first array of memory cells if locations are available in the second array of memory cells by moving data from the first array of memory cells to the second array of memory cells. - View Dependent Claims (17, 18, 19, 20)
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21. An electronic system comprising:
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a host that generates memory device control signals; and a memory device, coupled to the host and configured to receive the memory device control signals, the memory device comprising; a first array of memory cells each memory cell having a first density; a second array of memory cells each memory cell having a second density; and control circuitry, wherein the control circuitry is configured to store data in the first array of memory cells or the second array of memory cells based on interpreting a tracked history of received write operations issued to logical addresses of said data and wherein the control circuitry is further configured to maintain at least a particular number of spare locations in the first array of memory cells if locations are available in the second array of memory cells by moving data from the first array of memory cells to the second array of memory cells. - View Dependent Claims (22, 23, 24, 25, 26)
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27. An electronic system comprising:
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a host that generates memory device control signals; and a memory device, coupled to the host and configured to receive the memory device control signals, the memory device comprising; a first array of memory cells each memory cell having a first density; a second array of memory cells each memory cell having a second density; and control circuitry, wherein the control circuitry is configured to store data in the first array of memory cells or the second array of memory cells based on interpreting a tracked history of received write operations issued to logical addresses of said data; wherein the host is configured to perform a boot load operation; and wherein the control circuitry is further configured to store data in the first array of memory cells or the second array of memory cells based at least in part on if the logical address associated with the data is accessed during the boot load operation.
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28. A memory device comprising:
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a first array of memory cells each memory cell having a first density; a second array of memory cells each memory cell having a second density; and control circuitry, wherein the control circuitry is configured to determine usage data of a logical address in the memory device and store data associated with the logical address in one of the first array and second array of memory cells at least partially based on the usage and wherein the control circuitry is further configured to maintain at least a particular number of spare locations in the first array of memory cells if locations are available in the second array of memory cells by moving data from the first array of memory cells to the second array of memory cells. - View Dependent Claims (29, 30, 31, 32)
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33. A method for managing data stored on a memory device comprising a first array of memory cells each memory cell having a first density and a second array of memory cells each memory cell having a second density greater than the first density, the method comprising:
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determining whether a logical address is accessed during a particular time period following power up of the memory device; and storing data associated with the logical address in the first array of memory cells if it is determined that the logical address is accessed during the particular time period. - View Dependent Claims (34, 35, 36)
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Specification