Memory systems and memory modules

• US 8,060,774 B2
• Filed: 06/14/2007
• Issued: 11/15/2011
• Est. Priority Date: 06/24/2005
• Status: Active Grant

• Current Assignee: Google LLC (Alphabet Inc.)
• Original Assignee: Google Inc. (Alphabet Inc.)
• Inventors: Smith, Michael John Sebastian, Rajan, Suresh Natarajan
• Primary Examiner(s): Baderman; Scott T
• Assistant Examiner(s): PATEL, KAMINI B
• Application Number:
  US11/763,365
• Publication Number:
  US 20080010435A1
• Time in Patent Office: 1,615 Days
• Field of Search: 714/42, 714 7- 8, 714/710
• US Class Current: 714/5
• CPC Class Codes: G01K 13/00 Thermometers specially adapted for specific purposes
• CPC Class Codes: G06F 11/1076 Parity data used in redundant arrays of independent storages, e.g. in RAID systems
• CPC Class Codes: G06F 11/26 Functional testing
• CPC Class Codes: G06F 12/00 Accessing, addressing or allocating within memory systems or architectures digital input from, or digital output to record carriers, e.g. to disk storage units, G06F3/06
• CPC Class Codes: G06F 13/1668 Details of memory controller
• CPC Class Codes: G06F 15/7821 Tightly coupled to memory, e.g. computational memory, smart memory, processor in memory
• CPC Class Codes: G06F 17/00 Digital computing or data processing equipment or methods, specially adapted for specific functions information retrieval, database structures or file system structures therefor G06F16/00
• CPC Class Codes: G11C 11/401 forming cells needing refreshing or charge regeneration, i.e. dynamic cells
• CPC Class Codes: G11C 11/4076 Timing circuits for regeneration management G11C11/406
• CPC Class Codes: G11C 11/4093 Input/output [I/O] data interface arrangements, e.g. data buffers
• CPC Class Codes: G11C 2207/2254 Calibration
• CPC Class Codes: G11C 29/02 Detection or location of defective auxiliary circuits, e.g. defective refresh counters
• CPC Class Codes: G11C 29/022 in I/O circuitry
• CPC Class Codes: G11C 29/028 with adaption or trimming of parameters
• CPC Class Codes: G11C 29/24 Accessing extra cells, e.g. dummy cells or redundant cells
• CPC Class Codes: G11C 29/50 Marginal testing, e.g. race, voltage or current testing
• CPC Class Codes: G11C 29/50012 of timing
• CPC Class Codes: G11C 7/10 Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
• CPC Class Codes: G11C 7/1012 Data reordering during input/output, e.g. crossbars, layers of multiplexers, shifting or rotating
• CPC Class Codes: G11C 7/1045 Read-write mode select circuits
• CPC Class Codes: G11C 8/12 : Group selection circuits, e.g. for memory block selection, chip selection, array selection
• CPC Class Codes: H01L 2224/16145 : the bodies being stacked
• CPC Class Codes: H01L 2224/16225 : the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA

Abstract

One embodiment of the present invention sets forth a memory module that includes at least one memory chip, and an intelligent chip coupled to the at least one memory chip and a memory controller, where the intelligent chip is configured to implement at least a part of a RAS feature. The disclosed architecture allows one or more RAS features to be implemented locally to the memory module using one or more intelligent register chips, one or more intelligent buffer chips, or some combination thereof. Such an approach not only increases the effectiveness of certain RAS features that were available in prior art systems, but also enables the implementation of certain RAS features that were not available in prior art systems.

Claims

1. A memory module, comprising:

at least one memory chip; and

a first intelligent chip coupled to the at least one memory chip and adapted to be coupled to a memory controller, wherein the first intelligent chip is configured to implement at least a part of a reliability and serviceability (RAS) feature; and

a second intelligent chip coupled to the at least one memory chip and adapted to be coupled to the memory controller, and a sideband bus that couples the first intelligent chip to the second intelligent chip, wherein the second intelligent chip is configured to transmit a signal to the first intelligent chip to turn off an output buffer associated with the first intelligent chip.

2. The memory module of claim 1, wherein the first intelligent chip is configured to control a light-emitting diode to indicate a failure of the memory module.

3. The memory module of claim 1, wherein the RAS feature comprises a self-test performed on the memory module.

4. The memory module of claim 3, wherein the first intelligent chip is configured to control one or more light-emitting diodes to indicate a failed or successful self-test.

5. The memory module of claim 1, wherein the RAS feature comprises memory sparing.

6. The memory module of claim 5, wherein the first intelligent chip is configured to calculate replacement possibilities, optimize a replacement based on a replacement strategy, notify a host system of memory sparing operations being performed, and perform a memory sparing substitution or replacement.

7. The memory module of claim 1, wherein the RAS feature comprises memory mirroring.

8. The memory module of claim 1, wherein the RAS feature comprises memory redundant array of inexpensive disks (RAID) functionality.

9. The memory module of claim 1, wherein the RAS feature comprises memory defect remapping.

10. The memory module of claim 1, wherein the RAS feature comprises memory status and information reporting.

11. The memory module of claim 1, wherein the RAS feature comprises memory temperature monitoring.

12. The memory module of claim 1, wherein the RAS feature comprises thermal control functionality.

13. The memory module of claim 1, wherein the RAS feature comprises memory failure reporting.

14. The memory module of claim 1, wherein the RAS feature comprises memory access pattern gathering and reporting.

15. The memory module of claim 1, wherein the RAS feature comprises performance control functionality based on memory access patterns.

16. The memory module of claim 1, wherein the RAS feature comprises byte-level check coding.

17. The memory module of claim 1, wherein the RAS feature comprises checkpointing.

18. The memory module of claim 1, wherein the RAS feature comprises read retry detection.

19. The memory module of claim 1, wherein the RAS feature comprises hot-plug or hot-swap functionality.

20. The memory module of claim 1, further comprising at least one redundant data path to or from the first intelligent chip.

21. The memory module of claim 1, wherein the RAS feature comprises autonomous refresh functionality.

22. The memory module of claim 1, wherein the RAS feature comprises patrol or demand scrubbing.

23. The memory module of claim 1, wherein the first intelligent chip is configured to transmit or receive one or more parity-protected signals.

24. The memory module of claim 1, wherein the RAS feature comprises error correction code (ECC) signaling.

25. The memory module of claim 1, further comprising a serial presence detect (SPD) chip, and wherein the RAS feature comprises sideband signaling between the memory module and the memory controller using the SPD chip.

26. The memory module of claim 1, further comprising at least one alternative data path between the first intelligent chip and the at least one memory chip, and wherein the RAS feature comprises bypass and data recovery using the alternative data path.

27. The memory module of claim 1, wherein the RAS feature comprises thermal or power control functionality at a sub-memory module level.

28. The memory module of claim 1, wherein the memory module comprises a dual inline memory module (DIMM).

29. The memory module of claim 1, wherein the at least one memory chip comprises a stack of dynamic random access memory chips.

30. The memory module of claim 1, wherein the second intelligent chip is configured to implement another part of the RAS feature.

31. The memory module of claim 1, wherein the memory module is part of a memory subsystem.

32. The memory module of claim 1, wherein the memory module is coupled to a motherboard.

33. The memory module of claim 1, wherein the memory module is included in a computer system.

34. The memory module of claim 1, wherein the first intelligent chip is an intelligent buffer chip, and the second intelligent chip is an intelligent register chip.

35. The memory module of claim 1, wherein the sideband bus is configured to communicate control information, wherein the control information includes an indication of a data flow direction, at least one port identifier, and an indication of a number of byte lanes per port.

36. The memory module of claim 1, wherein the sideband bus is configured to communicate control information in the form of a fixed-format command packet.

37. The memory module of claim 36, wherein the command packet is two cycles long, a command type is transmitted in a first cycle, and a value associated with a command of the command type is transmitted in a second cycle.

38. The memory module of claim 1, wherein the sideband bus is configured to communicate information to configure a bi-directional multiplexer/de-multiplexer on the first intelligent chip or the second intelligent chip.

39. The memory module of claim 1, wherein the sideband bus is configured to communicate information to prompt the first intelligent chip or the second intelligent chip to use a look-aside buffer to substitute data from good memory bits in the at least one memory chip for data from known bad memory bits in the at least one memory chip.

40. The memory module of claim 1, wherein the sideband bus is configured to transfer mode register commands transmitted by the memory controller.

41. The memory module of claim 40, wherein the sideband bus is configured to modify one or more values previously written to one or more mode registers.

42. The memory module of claim 1, wherein the sideband bus is configured to communicate translation and mapping functions between the first intelligent chip and the second intelligent chip.

43. The memory module of claim 1, wherein the sideband bus is configured as a time-domain multiplexed address bus.

44. The memory module of claim 25, wherein the first intelligent chip and the second intelligent chip are configured to communicate through the SPD chip.

45. The memory module of claim 34, wherein the second intelligent chip is configured to modify a command that configures an on-die termination resistance value.

46. The memory module of claim 45, wherein the sideband bus is configured to communicate the command that configures the on-die termination resistance value.

47. The memory module of claim 34, wherein the first intelligent chip includes a bi-directional multiplexer/de-multiplexer.

48. The memory module of claim 47, wherein the sideband bus is configured to communicate control information that includes commands for controlling the bi-directional multiplexer/de-multiplexer.

49. The memory module of claim 48, wherein the bi-directional multiplexer/de-multiplexer is a four-port-to-one-port structure or a two-port-to-one-port structure.

50. The memory module of claim 34, wherein the sideband bus is configured to communicate control information that includes commands for controlling a direction of data flow to or from the first intelligent chip.

51. The memory module of claim 41, wherein the second intelligent chip is configured to modify a mode register command to configure an on-die termination resistance value.