Evaluation circuit and method for detecting and/or locating faulty data words in a data stream Tn
First Claim
1. An evaluation circuit for detecting and/or locating faulty data words in a data stream Tn comprising:
- a first linear automaton circuit and a second linear automaton circuit connected in parallel, each having a set of states, wherein the first linear automaton circuit and the second linear automaton circuit each have inputs that are commonly connected for receiving a data stream Tn comprising n successive data words y(1), . . . , y(n) each having a width of k bits, k>
1,wherein the first linear automaton circuit can be described by the following equation
z(t+1)=Az(t)⊕
y(t)wherein the second linear automaton circuit can be described by the following equation
z(t+1)=Bz(t)⊕
y(t)where z represents state vectors and A and B represent the state matrices of the linear automaton circuits, where the state matrices A and B can be inverted, and where a dimension L of the state vectors z is ≧
k, wherein A≠
B,the first linear automaton circuit and the second linear automaton circuit are designed such that a first signature and a second signature, respectively, is calculated of each data word of the n successive data words y(1), . . . , y(n),L first logic combination gates arranged downstream of the first linear automaton circuit and also L second logic combination gates arranged downstream of the second linear automaton circuit,the logic combination gates are designed such that the signature respectively calculated by the linear automaton circuit can be compared with a predeterminable good signature and a comparison value can be output.
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Abstract
An evaluation circuit and method for detecting faulty data words in a data stream is disclosed. In one embodiment the evaluation circuit according to the invention includes a first linear automaton circuit and also a second linear automaton circuit connected in parallel, each having a set of states z, which have a common input line for receiving a data stream Tn. The first linear automaton circuit and the second linear automaton circuit are designed such that a first signature and a second signature, respectively, can be calculated. Situated downstream of the two linear automaton circuits are respectively a first logic combination gate and a second logic combination gate, which compare the signature respectively calculated by the linear automaton circuit with a predeterminable good signature and output a comparison value.
14 Citations
23 Claims
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1. An evaluation circuit for detecting and/or locating faulty data words in a data stream Tn comprising:
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a first linear automaton circuit and a second linear automaton circuit connected in parallel, each having a set of states, wherein the first linear automaton circuit and the second linear automaton circuit each have inputs that are commonly connected for receiving a data stream Tn comprising n successive data words y(1), . . . , y(n) each having a width of k bits, k>
1,wherein the first linear automaton circuit can be described by the following equation
z(t+1)=Az(t)⊕
y(t)wherein the second linear automaton circuit can be described by the following equation
z(t+1)=Bz(t)⊕
y(t)where z represents state vectors and A and B represent the state matrices of the linear automaton circuits, where the state matrices A and B can be inverted, and where a dimension L of the state vectors z is ≧
k, wherein A≠
B,the first linear automaton circuit and the second linear automaton circuit are designed such that a first signature and a second signature, respectively, is calculated of each data word of the n successive data words y(1), . . . , y(n), L first logic combination gates arranged downstream of the first linear automaton circuit and also L second logic combination gates arranged downstream of the second linear automaton circuit, the logic combination gates are designed such that the signature respectively calculated by the linear automaton circuit can be compared with a predeterminable good signature and a comparison value can be output. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 20, 21, 22, 23)
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19. A method for detecting and/or locating faulty data words in a data stream Tn, the method having the following method steps of:
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inputting data words y(1), . . . , y(i−
1), y′
(i), y(i+1), . . . , y(n) of a data stream Tn into a first coder, each data word having a width of k bits, k>
1,encoding the data words y(1), . . . , y(n) into coded data words u1(1), . . . , u1(n) having a word width K1 where K1≧
k by means of the coding function Cod1 of the first coder,inputting the coded data words u1(1), . . . , u1(i−
1), u1′
(i) or u1(i), u1(i), . . . , u1(n) into the inputs of a first linear automaton circuit, which is described by the automaton equation;
z1(t+1)=A·
z1(t)+u1(t)where t is an instant in time, z1 represents a K1-dimensional state vector and A represents a K1×
K1 state matrix, and where the state matrix A can be inverted,processing the coded data words u1(1), . . . , u1(i−
1), u1′
(i) or u1(i), u1(i), . . . , u1(n) by means of the first linear automaton circuit, the first linear automaton circuit,undergoing transition to the state z1(n+1)=S1(L1, y(1), . . . , y(i−
1), y(i), y(i+1), . . . , y(n)) if no error can be detected in the case of the coded data words u1(1), . . . , u1(i−
1), u1(i), u1(i+1), . . . , u1(n),undergoing transition to the state z1′
(n+1)=S1(L1, y(1), . . . , y(i−
1), y′
(i), y(i+1), . . . , y(n)) if an error is present at least in the case of the i-th position of the coded data words u1(1), . . . , u1(i−
1), u1′
(i), . . . , u1(n),the signature of an error-free data stream Tn being designated by S(L1, y(1), . . . , y(i−
1), y(i), y(i+1), . . . , y(n)) and the signature of a faulty data stream Tn being designated by S(L1, y(1), . . . , y(i−
1), y′
(i), y(i+1), . . . , y(n)),checking the determined signature of the data stream Tn and continuing with method step a) for further data streams Tn if the determined signature of the data stream Tn is the signature of an error-free data stream Tn, inputting the data words y(1), . . . , y(i−
1), y′
(i), . . . , y(n) of the data stream Tn in a second coder,coding the data words y(1), . . . , y(i−
1), y′
(i), y(i+1), . . . , y(n) to coded data words u2(1), . . . , u2(i−
1), u2′
(i) or u2(i), u2(i), . . . , u2(n) having the word width K2 where K2≧
k by means of the coding function Cod2 of the second coder,inputting the coded data words u2(1), . . . , u2(i−
1), u2′
(i) or u2(i), u2(i), . . . , u2(n) into the inputs of a second linear automaton circuit, which is described by the automaton equation
z2(t+1)=B·
z2(t)⊕
u2(t)where z2 represents a K2-dimensional state vector and B represents a K2×
K2 state matrix where B≠
A, and where the state matrix B can be inverted,processing the coded data words u2(1), . . . , u2(i−
1), u2′
(i) or u2(i), u2(i), . . . , u2(n) by means of the second linear automaton circuit, the second linear automaton circuit,undergoing transition to the state z2(n+1)=S2(L2, y(1), . . . , y(i−
1), y(i), y(i+1), . . . , y(n)) if no error can be detected in the case of the data words u2(1), . . . , u2(i−
1), u2(i), u2(i), . . . , u2(n),undergoing transition to the state z2′
(n+1)=S2(L2, y(1), . . . , y(i−
1), y(i), y′
(i), y(i+1), . . . , y(n)) if an error is present at least in the case of the i-th position of the coded data words u2(1), . . . , u2(i−
1), u2′
(i), u2(i), . . . , u2(n),the signature of an error-free data stream Tn being designated by S(L2, y(1), . . . , y(i−
1), y(i), y(i+1), . . . , y(n)) and the signature of a faulty data stream Tn being designated by S(L2, y(1), . . . , y(i−
1), y′
(i), . . . , y(n)),determining the signature differences Δ
S1 and Δ
S2 by means of exclusive-OR logic combinations of the signatures S1 and S2 ascertained good signatures, in each case according to the following specifications;
Δ
S1=S(L1,y(1), . . . , y(i−
1), y(i),y(i+1), . . . , y(n))
⊕
S(L2,y(1), . . . , y(i−
1),y′
(i),y(i+1), . . . , y(n))
Δ
S2=S(L2,y(1), . . . , y(i−
1), y(i),y(i+1), . . . , y(n))
⊕
S(L2,y(1), . . . y(i−
1),y′
(i),y(i+1), . . . , y(n))determining a unique solution for the position i of the faulty bit in the faulty data word by solving the equation
ƒ
1−
1(Ai−
nΔ
S1)=ƒ
2−
1(Bi−
nΔ
S2)and if no unique solution results for 1≦
i≦
n, outputting a notification by means of an output medium that two or more errors are present in the data stream Tn under consideration,determining a unique solution for the counter e(i) of the faulty data word y′
(i) in the data stream Tn by solving the equation
e(i)=ƒ
1−
1(Ai−
nΔ
S1)outputting the position i of the faulty bit in the faulty data word and also the error e(i) of the faulty data word y′
(i) in the data stream Tn by means of an output medium; andevaluating an integrated circuit in response to the output.
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Specification