Method of producing a plate-shaped structure, in particular, from silicon, use of said method and plate-shaped structure thus produced, in particular from silicon

• US 8,062,564 B2
• Filed: 09/23/2004
• Issued: 11/22/2011
• Est. Priority Date: 09/30/2003
• Status: Active Grant

• Current Assignee: Soitec S.A.
• Original Assignee: Soitec Silicon On Insulator Technologies SA (Soitec S.A.)
• Inventors: Bruel, Michel
• Primary Examiner(s): Johnson; Christina
• Assistant Examiner(s): Khare; Atul P
• Application Number:
  US10/574,120
• Publication Number:
  US 20080038564A1
• Time in Patent Office: 2,616 Days
• Field of Search: 264/41, 264/51, 264/345, 264/346, 438/458, 438/455, 156/249
• US Class Current: 264/51
• CPC Class Codes: C30B 29/06 Silicon
• CPC Class Codes: C30B 33/02 Heat treatment C30B33/04, C30B33/06 take precedence
• CPC Class Codes: H01L 21/76254 with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond

Abstract

Method for fabricating a structure in the form of a plate, and structure in the form of a plate, in particular formed from silicon, including at least one substrate, a superstrate and at least one intermediate layer interposed between the substrate and the superstrate, in which the intermediate layer comprises at least one base material having distributed therein atoms or molecules termed extrinsic atoms or molecules which differ from the atoms or molecules of the base material, and in which a heat treatment is applied to said plate so that, in the temperature range of said heat treatment, the intermediate layer is plastically deformable and the presence of the selected extrinsic atoms or molecules in the selected base material causes the irreversible formation of micro-bubbles or micro-cavities in the intermediate layer.

Claims

1. A method for fabricating a silicon wafer, which method comprises:

depositing at least one intermediate layer on either of a substrate and/or a superstrate by chemical vapor deposition, wherein the intermediate layer is deposited as a glass comprising at least one base material having distributed therein extrinsic atoms or molecules which differ from those of the base material;

assembling the substrate and the superstrate so that the as-deposited intermediate layer is interposed between the substrate and the superstrate to form a silicon wafer structure; and

applying a heat treatment to the resulting structure in a temperature range that causes the intermediate layer to become spongy and plastically deformable with the as-deposited extrinsic atoms or molecules in the base material causing an irreversible formation of microbubbles or microcavities in the intermediate layer resulting from the heat treatment in a configuration and amount which weakens the intermediate layer.

2. The method as claimed in claim 1, which further comprises continuing the heat treatment until it produces a rupture of the intermediate layer and, as a result, separation of the substrate and the superstrate.

3. The method as claimed in claim 1, which further comprises applying forces between the substrate and the superstrate to bring about the rupture of the intermediate layer between the substrate and the superstrate due to the presence of the microbubbles or microcavities.

4. The method as claimed in claim 1, which further comprises chemically attacking the intermediate layer of the structure so as to separate the substrate and the superstrate.

5. The method as claimed in claim 1, wherein the intermediate layer increases in its thickness subsequent to the heat treatment as compared to its thickness prior to the heat treatment by as much as a factor of 3.

6. The method as claimed in claim 1, wherein after the heat treatment, at least some of the microbubbles or microcavities have a volume such that they are open both on the substrate and on the superstrate side, or furthermore that they are mutually open to constitute channels which are open between the side ends of the intermediate layer.

7. The method as claimed in claim 6, which further comprises providing projecting portions in the substrate or superstrate which constitute notches that facilitate the formation of the channels.

8. The method as claimed in claim 6, which further comprises cooling the structure by circulating a cooling fluid through the channels formed by the microbubbles or microcavities.

9. The method as claimed in claim 6, which further comprises introducing a solution of acid into the channels to chemically attack the intermediate layer.

10. The method as claimed in claim 1, which further comprises reducing the thickness of the superstrate or substrate.

11. The method as claimed in claim 1, wherein the substrate and the superstrate are formed from monocrystalline silicon.

12. The method as claimed in claim 1, wherein the base material comprises silica and the extrinsic atoms comprise atoms of phosphorus, thus forming an intermediate layer of phospho-silicate glass.

13. The method as claimed in claim 12, wherein the extrinsic atoms further comprise atoms of boron, thus forming an intermediate layer of boro-phospho-silicate glass.

14. The method as claimed in claim 13, wherein the concentration of phosphorus is in the range from 6% to 14%.

15. The method as claimed in claim 13, wherein the concentration of boron is in the range from 0% to 4%.

16. The method as claimed in claim 1, wherein the heat treatment is carried out at a temperature in the range from 900°

C. to 1200°

C.

17. The method as claimed in claim 1, wherein the step of assembling further comprises attaching the superstrate or substrate to the intermediate layer by molecular wafer bonding.

18. The method as claimed in claim 17, which further comprises, prior to the step of assembling, providing a thermal silicon oxide on either of the substrate or superstrate that does not include the intermediate layer.

19. The method as claimed in claim 17, which further comprises, prior to the step of depositing, providing a thermal silicon oxide on each of the substrate and superstrate so that the intermediate layer is deposited on the thermal silicon oxide on either of the substrate or the superstrate.

20. The method as claimed in claim 1, which further comprises fabricating the plate as a silicon on insulator plate for the further fabrication of integrated electronic circuits or integrated opto-electronic circuits thereon.