Semiconductor device and method of stacking same size semiconductor die electrically connected through conductive via formed around periphery of the die

• US 8,062,929 B2
• Filed: 05/27/2010
• Issued: 11/22/2011
• Est. Priority Date: 05/04/2007
• Status: Active Grant

• Current Assignee: JCET Semiconductor (Shaoxing) Co., Ltd.
• Original Assignee: Stats Chippac Limited
• Inventors: Do, Byung Tai, Kuan, Heap Hoe, Chow, Seng Guan
• Primary Examiner(s): Pizarro Crespo; Marcos D
• Assistant Examiner(s): Vieira; Diana C
• Application Number:
  US12/788,785
• Publication Number:
  US 20100233852A1
• Time in Patent Office: 544 Days
• Field of Search: 257/684, 257/690, 257/700, 257/691, 257/723, 257/724, 257/731, 257E23001-E23004, 257/E23.01, 257/E23.011, 257/E23.79, 257/E23.116, 257E23123-E23134, 257E23141-E23168, 257/678, 257/685, 257/686, 257/701, 257/730, 257/E23.003, 257/E23.129, 257/E23.133, 438/107, 438/109, 438/127, 438/110, 438/111, 438/112, 438/113, 438/125, 438/126
• US Class Current: 438/109
• CPC Class Codes: H01L 21/6835 using temporarily an auxiliary support
• CPC Class Codes: H01L 21/6836 Wafer tapes, e.g. grinding or dicing support tapes adhesive tapes in general C09J7/20
• CPC Class Codes: H01L 21/78 with subsequent division of the substrate into plural individual devices cutting to change the surface-physical characteristics or shape of semiconductor bodies H01L21/304
• CPC Class Codes: H01L 2221/68327 used during dicing or grinding
• CPC Class Codes: H01L 2221/68336 involving stretching of the auxiliary support post dicing
• CPC Class Codes: H01L 2224/02371 connecting the bonding area on a surface of the semiconductor or solid-state body with another surface of the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/04105 Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
• CPC Class Codes: H01L 2224/18 High density interconnect [HDI] connectors; Manufacturing methods related thereto
• CPC Class Codes: H01L 2224/45015 being circular
• CPC Class Codes: H01L 2224/45099 Material
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48145 the bodies being stacked
• CPC Class Codes: H01L 2224/48472 the other connecting portion not on the bonding area also being a wedge bond, i.e. wedge-to-wedge
• CPC Class Codes: H01L 2224/73265 Layer and wire connectors
• CPC Class Codes: H01L 2224/82 by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
• CPC Class Codes: H01L 2224/82039 using a laser
• CPC Class Codes: H01L 2224/97 the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 2225/06506 Wire or wire-like electrical connections between devices
• CPC Class Codes: H01L 2225/0651 Wire or wire-like electrical connections from device to substrate
• CPC Class Codes: H01L 2225/06513 Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
• CPC Class Codes: H01L 2225/06541 : Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV] manufacturing via connections per se H01L21/76898
• CPC Class Codes: H01L 2225/06551 : Conductive connections on the side of the device
• CPC Class Codes: H01L 2225/06582 : Housing for the assembly, e.g. chip scale package [CSP]
• CPC Class Codes: H01L 2225/1035 : the device being entirely enclosed by the support, e.g. high-density interconnect [HDI]
• CPC Class Codes: H01L 2225/1052 : Wire or wire-like electrical connections
• CPC Class Codes: H01L 2225/1094 : Thermal management, e.g. cooling
• CPC Class Codes: H01L 23/3114 : the device being a chip scale package, e.g. CSP
• CPC Class Codes: H01L 23/3128 : the substrate having spherical bumps for external connection
• CPC Class Codes: H01L 23/3185 : the coating covering also the sidewalls of the semiconductor body
• CPC Class Codes: H01L 23/49551 : characterised by bent parts
• CPC Class Codes: H01L 23/49575 : Assemblies of semiconductor devices on lead frames
• CPC Class Codes: H01L 23/49805 : the leads being also applied on the sidewalls or the bottom of the substrate, e.g. leadless packages for surface mounting
• CPC Class Codes: H01L 23/5389 : the chips being integrally enclosed by the interconnect and support structures
• CPC Class Codes: H01L 24/25 : of a plurality of high density interconnect connectors
• CPC Class Codes: H01L 24/48 : of an individual wire connector
• CPC Class Codes: H01L 24/82 : by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI] interconnection structure between a plurality of semiconductor chips H01L23/5389
• CPC Class Codes: H01L 24/96 : the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
• CPC Class Codes: H01L 24/97 : the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 25/03 : all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
• CPC Class Codes: H01L 25/0657 : Stacked arrangements of devices
• CPC Class Codes: H01L 25/105 : the devices being of a type provided for in group H01L27/00
• CPC Class Codes: H01L 25/50 : Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01027 : Cobalt [Co]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01074 : Tungsten [W]
• CPC Class Codes: H01L 2924/01075 : Rhenium [Re]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/09701 : Low temperature co-fired ceramic [LTCC]
• CPC Class Codes: H01L 2924/15153 : the die mounting substrate comprising a recess for hosting the device
• CPC Class Codes: H01L 2924/1517 : Multilayer substrate
• CPC Class Codes: H01L 2924/15173 : in a single layer of the multilayer substrate
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/15313 : being a land array, e.g. LGA
• CPC Class Codes: H01L 2924/1532 : the connection portion being formed on the die mounting surface of the substrate
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/19107 : off-chip wires
• CPC Class Codes: H01L 2924/207 : Diameter ranges
• CPC Class Codes: H01L 2924/3511 : Warping

Abstract

A semiconductor device has a plurality of similar sized semiconductor die each with a plurality of bond pads formed over a surface of the semiconductor die. An insulating layer is formed around a periphery of each semiconductor die. A plurality of conductive THVs is formed through the insulating layer. A plurality of conductive traces is formed over the surface of the semiconductor die electrically connected between the bond pads and conductive THVs. The semiconductor die are stacked to electrically connect the conductive THVs between adjacent semiconductor die. The stacked semiconductor die are mounted within an integrated cavity of a substrate or leadframe structure. An encapsulant is deposited over the substrate or leadframe structure and the semiconductor die. A thermally conductive lid is formed over a surface of the substrate or leadframe structure. The stacked semiconductor die are attached to the thermally conductive lid.

Claims

1. A method of making a semiconductor device, comprising:

providing a plurality of semiconductor dies each having a plurality of bond pads formed over a surface of the semiconductor die;

forming an insulating layer around a periphery of each semiconductor die with a first surface and second surface of the semiconductor die opposite the first surface remaining devoid of the insulating layer;

forming a plurality of conductive vias through the insulating layer;

stacking the semiconductor die to electrically connect the conductive vias between adjacent semiconductor die with the first surface of a first semiconductor die of the stacked semiconductor dies contacting the second surface of a second semiconductor die of the stacked semiconductor dies; and

depositing an encapsulant over the semiconductor die.

2. The method of claim 1, further including forming a plurality of conductive traces over the surface of the semiconductor die electrically connected between the bond pads and conductive vias.

3. The method of claim 1, further including:

providing a substrate or leadframe structure having an integrated cavity; and

mounting the stacked semiconductor dies within a portion of the integrated cavity prior to depositing the encapsulant.

4. The method of claim 3, further including forming a bond wire between a first die of the plurality of semiconductor dies and the substrate or leadframe structure.

5. The method of claim 3, further including:

forming a thermally conductive lid over a surface of the substrate or leadframe structure; and

attaching the stacked semiconductor dies to the thermally conductive lid.

6. The method of claim 1, further including stacking a plurality of the semiconductor devices.

7. The method of claim 1, wherein each of the plurality of semiconductor dies has a substantially similar footprint.

8. A method of making a semiconductor device, comprising:

providing a plurality of semiconductor dies each having a plurality of bond pads formed on an active surface of the semiconductor dies;

providing a carrier;

mounting the plurality of semiconductor dies to the carrier with a back surface of the plurality of semiconductor dies opposite the active surface oriented to the carrier;

forming an insulating layer around a periphery of each semiconductor die with the active surface and back surface remaining devoid of the insulating layer;

forming a plurality of conductive vias through the insulating layer;

forming a plurality of conductive traces on the active surface of the semiconductor die electrically connected between the bond pads and conductive vias;

removing the carrier;

stacking the semiconductor dies to electrically connect the conductive vias between adjacent semiconductor die with the back surface of a first semiconductor die of the stacked semiconductor dies directly contacting the active surface of a second semiconductor die of the stacked semiconductor dies; and

depositing an encapsulant over the semiconductor dies.

9. The method of claim 8, further including:

providing a substrate or leadframe structure having an integrated cavity; and

mounting the stacked semiconductor dies within a portion of the integrated cavity prior to depositing the encapsulant.

10. The method of claim 9, further including forming a bond wire between a first die of the plurality of semiconductor dies and the substrate or leadframe structure.

11. The method of claim 9, further including forming a bond wire between a first die of the plurality of semiconductor dies and a terminal land.

12. The method of claim 9, further including:

forming a thermally conductive lid over a surface of the substrate or leadframe structure; and

attaching the stacked semiconductor dies to the thermally conductive lid.

13. The method of claim 8, further including stacking a plurality of the semiconductor devices.

14. The method of claim 8, wherein each of the plurality of semiconductor dies has a substantially similar footprint.

15. A method of making a semiconductor device, comprising:

providing a plurality of semiconductor dies each having a plurality of bond pads formed on an active surface of the semiconductor die;

providing a carrier;

mounting the plurality of semiconductor dies to the carrier with a back surface of the plurality of semiconductor dies opposite the active surface oriented to the carrier;

forming an insulating layer around a periphery of each semiconductor die with the active surface and back surface remaining devoid of the insulating layer;

forming a plurality of conductive through-hole vias (THVs) through the insulating layer;

forming a plurality of conductive traces on the active surface of the semiconductor die electrically connected between the bond pads and conductive THVs;

removing the carrier;

stacking the semiconductor dies to directly electrically connect the conductive THVs between adjacent semiconductor die with the back surface of a first semiconductor die of the stacked semiconductor dies directly contacting the active surface of a second semiconductor die of the stacked semiconductor dies;

providing a substrate or leadframe structure having an integrated cavity;

mounting the stacked semiconductor dies within a portion of the integrated cavity; and

depositing an encapsulant over the substrate or leadframe structure and the semiconductor dies.

16. The method of claim 15, further including forming a bond wire between a first die of the plurality of semiconductor dies and the substrate or leadframe structure.

17. The method of claim 15, further including forming a bond wire between a first die of the plurality of semiconductor dies and a terminal land.

18. The method of claim 15, further including forming a thermally conductive lid over a surface of the substrate or leadframe structure.

19. The method of claim 18, further including attaching the stacked semiconductor dies to the thermally conductive lid.

20. The method of claim 15, further including stacking a plurality of the semiconductor devices.