Method for manufacturing a field plate in a trench of a power transistor

• US 8,062,954 B2
• Filed: 04/21/2009
• Issued: 11/22/2011
• Est. Priority Date: 05/23/2008
• Status: Active Grant

• Current Assignee: Infineon Technologies AG
• Original Assignee: Infineon Technologies AG
• Inventors: Poelzl, Martin
• Primary Examiner(s): Wilczewski; Mary
• Assistant Examiner(s): THOMAS, TONIAE M
• Application Number:
  US12/427,098
• Publication Number:
  US 20090291543A1
• Time in Patent Office: 945 Days
• Field of Search: 438/431, 438/432, 438/454, 438/589, 438/270, 257/E21.41, 257/E21.547
• US Class Current: 438/432
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

A method for manufacturing a field plate in a trench of a power transistor in a substrate of a first conductivity type is disclosed. The trench is formed in a first main surface of the substrate.

Claims

1. A method for manufacturing a field plate in a trench in a substrate, wherein the trench is formed in a first main surface of the substrate, the method comprising:

growing a field oxide layer over the first main surface of the substrate and side walls of the trench;

depositing polysilicon at least in the trench;

etching the polysilicon, wherein the polysilicon is etched in the trench up to a first level above a bottom of the trench;

thermally oxidizing the polysilicon in the trench and the field oxide layer on side walls of the trench, wherein the polysilicon oxide has a growth rate that is higher than a growth rate of the oxide on the side wall of the trench;

etching the polysilicon oxide in the trench and the oxide on the side walls of the trench, wherein the polysilicon oxide is removed by etching up to a top side of the polysilicon, such that the polysilicon remains up to a second level from the bottom of the trench, and the oxide on the side walls of the trench is etched to a third level from the bottom of the trench, the third level being as far or farther from the bottom of the trench than the second level; and

forming a gate oxide layer in the trench and on the first main surface of the substrate, wherein the polysilicon remaining in the trench below the gate oxide layer forms a field plate.

2. The method according to claim 1, wherein etching the polysilicon oxide in the trench and the oxide on the side walls of the trench is carried out such that remaining oxide is in planar alignment with a surface of the polysilicon.

3. The method according to claim 1, wherein etching the polysilicon oxide in the trench and the oxide on the side walls of the trench is carried out such that remaining oxide forms an angle with a surface of the polysilicon in the trench.

4. The method according to claim 3, wherein the angle is 0°

to 40°

.

5. The method according to claim 3, wherein the angle is 0°

to 25°

.

6. The method according to claim 1, wherein the growth rate of the polysilicon oxide is higher than the growth rate of the oxide on the side walls of the trench by a factor of up to 1.5.

7. The method according to claim 1, further comprising forming a drain at a surface of the substrate opposed to the first main surface.

8. A method for manufacturing a field plate in a trench of a power transistor in a substrate of a first conductivity type with a drain region, wherein the trench is formed in a first main surface of the substrate, the method comprising:

growing a field oxide layer on the first main surface of the substrate and side walls of the trench;

depositing polysilicon at least in the trench;

etching the polysilicon, wherein the polysilicon is etched in the trench up to a first level above a bottom of the trench;

thermally oxidizing the polysilicon in the trench and the field oxide layer on side walls of the trench, such that the polysilicon oxide has a growth rate that is higher than a growth rate of the oxide on the side walls of the trench;

etching the polysilicon oxide in the trench and the oxide on the side walls of the trench, wherein the polysilicon oxide is removed by etching up to a top side of the polysilicon, such that the polysilicon remains up to a second level from the bottom of the trench, and wherein the oxide on the side walls of the trench is etched to a third level from the bottom of the trench, the third level being as far or farther from the bottom of the trench than the second level, wherein the etching of the oxide on the side walls of the trench is carried out such that remaining oxide is in planar alignment with a surface of the polysilicon or forms an angle with a surface of the polysilicon in the trench; and

forming a gate oxide layer in the trench and on the first main surface of the substrate, such that the polysilicon remaining in the trench below the gate oxide layer forms a field plate.

9. The method according to claim 8, wherein the angle is 0°

to 40°

.

10. The method according to claim 8, wherein the angle is 0°

to 25°

.

11. The method according to claim 8, wherein the growth rate of the polysilicon oxide is higher than the growth rate of the oxide on the side walls of the trench by a factor of up to 1.5.

12. A method for manufacturing a field plate in a trench of a power transistor in a substrate of a first conductivity type with a drain region, wherein the trench is formed in a first main surface of the substrate, the method comprising:

growing a field oxide layer on the first main surface of the substrate and side walls of the trench;

depositing polysilicon at least in the trench;

etching the polysilicon, wherein the polysilicon is etched in the trench up to a predetermined first level above a bottom of the trench;

thermally oxidizing the polysilicon in the trench and the field oxide layer on side walls of the trench, wherein a growth rate of the polysilicon oxide is higher than a growth rate of the oxide on the side walls of the trench by a factor of up to 1.5;

etching the polysilicon oxide in the trench and the oxide on the side walls of the trench, wherein the polysilicon oxide is removed by etching up to a top side of the polysilicon, such that the polysilicon remains up to a second level from the bottom of the trench, and the oxide on the side walls of the trench is etched to a third level from the bottom of the trench, the third level being as far or farther from the bottom of the trench than the second level; and

forming a gate oxide layer in the trench and on the first main surface of the substrate, wherein the polysilicon remaining in the trench below the gate oxide layer forms a field plate.

13. The method according to claim 12, wherein etching the polysilicon oxide in the trench and the oxide on the side walls of the trench is carried out such that remaining oxide is in planar alignment with a surface of the polysilicon.

14. The method according to claim 12, wherein etching the polysilicon oxide in the trench and the oxide on the side walls of the trench is carried out such that remaining oxide forms an angle with a surface of the polysilicon in the trench.

15. The method according to claim 14, wherein the angle is 0°

to 40°

.

16. The method according to claim 14, wherein the angle is 0°

to 25°

.