Circuits and methods allowing for pixel array exposure pattern control

• US 8,063,350 B2
• Filed: 07/31/2008
• Issued: 11/22/2011
• Est. Priority Date: 08/03/2007
• Status: Expired due to Fees

• Current Assignee: Cognex Corporation, Teledyne Innovaciones Microelectronicas SL (Teledyne Technologies Incorporated)
• Original Assignee: Cognex Corporation
• Inventors: Dominguez-Castro, Rafael, Garcia, Alberto, McGarry, E. John
• Primary Examiner(s): Lee; John
• Application Number:
  US12/184,160
• Publication Number:
  US 20090072120A1
• Time in Patent Office: 1,209 Days
• Field of Search: 250/208.1, 257/69, 257/72, 257/258, 257/291, 257/292, 348/294, 348/302, 348/308, 382/312, 382/321
• US Class Current: 250/208.1
• CPC Class Codes: H04N 23/73 by influencing the exposure time
• CPC Class Codes: H04N 25/533 by using differing integration times for different sensor regions
• CPC Class Codes: H04N 25/583 with different integration times
• CPC Class Codes: H04N 25/75 Circuitry for providing, modifying or processing image signals from the pixel array

Abstract

An image processing system includes an image sensor circuit. The image sensor circuit is configured to obtain an image using a type of shutter operation in which an exposure pattern of a pixel array is set according to exposure information that changes over time based at least partially on charge accumulated in at least a portion of the pixel array. An image sensor circuit includes a pixel array and one or more circuits. The one or more circuits are configured to update exposure information based at least partially on one or more signals output from the pixel array, and to control an exposure pattern of the pixel array based on the exposure information. A pixel circuit includes a first transistor connected between a photodiode and a sense node, and a second transistor connected between an exposure control signal line and a gate of the first transistor.

Claims

1. An image sensor circuit, comprising:

a pixel array comprising a plurality of pixel circuits, wherein at least one of the plurality of pixel circuits includes a sense node whose voltage controls an output signal; and

one or more circuits configured to update exposure information based at least partially on one or more signals output from the pixel array, and configured to control an exposure pattern of the pixel array based on the exposure information, wherein said one or more circuits is configured to render a readout of the output signal nondestructive with respect to charge accumulating at the sense node.

2. The image sensor circuit of claim 1,

said one or more circuits configured to iteratively update the exposure information while an image is being captured by the pixel array based at least partially on the one or more signals output from the pixel array and at least one dilation rule.

3. The image sensor circuit of claim 2,

said at least one dilation rule specified by at least one structuring element.

4. The image sensor circuit of claim 1,

said plurality of pixel circuits controllable such that at least one pixel circuit in a row of the pixel array can integrate charge at a sense node of the pixel circuit while at least a second pixel circuit in said row is prevented from integrating charge at a sense node of said second pixel circuit during at least a portion of an image capture operation.

5. The image sensor circuit of claim 1,

said one or more circuits configured to iteratively update the exposure information based at least partially on values of the one or more signals output from the pixel array, said values of the one or more signals indicative of charge accumulated in at least a portion of the pixel array.

6. The image sensor circuit of claim 1,

said one or more circuits configured to individually control exposure states of the plurality of pixel circuits based on the exposure information so as to control the exposure pattern of the pixel array.

7. The image sensor circuit of claim 6,

said exposure states for each pixel circuit of the plurality of pixel circuits including an on-state in which the pixel circuit is allowed to integrate charge at a sense node of the pixel circuit and an off-state in which the pixel circuit is prevented from integrating additional charge at the sense node.

8. The image sensor circuit of claim 1, further comprising:

one or more memory devices for storing the exposure information as exposure pattern data including at least one bit for each pixel circuit of the plurality of pixel circuits to be used for controlling an exposure state of the pixel circuit.

9. The image sensor circuit of claim 8,

said one or more circuits configured to reset the exposure pattern data stored in the one or more memory devices to an initial pattern prior to an image capture operation.

10. The image sensor circuit of claim 1,

said one or more circuits configured to change the exposure pattern of the pixel array a plurality of times while an image is being captured by the pixel array based on the exposure information.

11. The image sensor circuit of claim 1, at least one pixel circuit of the plurality of pixel circuits comprising:

a light sensing element;

a first transistor having a terminal connected to the light sensing element; and

a second transistor connected between an exposure control signal line and a gate of the first transistor;

said one or more circuits configured to control a signal on the exposure control signal line based on the exposure information.

12. The image sensor circuit of claim 11, said at least one pixel circuit further comprising:

a third transistor connected to the light sensing element; and

a fourth transistor connected between an anti-blooming control signal line and a gate of the third transistor;

said one or more circuits configured to control an anti-blooming signal on the anti-blooming control signal line based on the exposure information.

13. The image sensor circuit of claim 12,

said one or more circuits configured to control the anti-blooming signal on the anti-blooming control signal line to be an opposite value of the exposure control signal on the exposure control signal line during an image capture operation.

14. The image sensor circuit of claim 12,

said light sensing element having a first portion that extends below the exposure control signal line and a second portion that extends below the anti-blooming control signal line.

15. The image sensor circuit of claim 11, said at least one pixel circuit further comprising:

one or more dummy diffusions that are connected to a constant voltage during an image capture operation.

16. The image sensor circuit of claim 11, said at least one pixel circuit further comprising:

a reset transistor connected between a fixed voltage and the sense node, a voltage at the sense node controlling an output signal;

said one or more circuits configured to control a reset signal that is applied to a gate of the reset transistor such that the reset transistor remains off during and between at least two readouts of the output signal during an image capture operation so as to render the at least two readouts of the output signal nondestructive with respect to charge accumulating at the sense node.

17. The image sensor circuit of claim 1,

said pixel array further comprising a plurality of column readout lines for providing the one or more signals;

and

said one or more circuits configured to selectively control signals on the plurality of column readout lines to be either voltage signals or current signals.

18. The image sensor circuit of claim 1,

wherein the one or more signals are analog current signals.

19. The image sensor circuit of claim 1, further comprising:

a column analog-to-digital converter circuit configured to receive analog signals output on a column readout line of the pixel array from two or more pixel circuits of the plurality of pixel circuits that are in a same column of the pixel array, and configured to convert the analog signals to corresponding digital signals.

20. The image sensor circuit of claim 1,

said plurality of pixel circuits arranged in a plurality of rows and a plurality of columns;

said one or more circuits configured to selectively control the pixel array to provide output from pixel circuits in two or more rows and two or more columns at a same time such that the outputs from the two or more rows combine in analog form on column readout lines of the pixel array.

21. The image sensor circuit of claim 1, further comprising:

a resistive grid including a plurality of switchable resistors and a plurality of capacitors, the plurality of capacitors connected to receive signals having values based on the one or more signals output from the pixel array, the plurality of switchable resistors configured to selectively connect the plurality of capacitors in accordance with command signals;

said one or more circuits configured to sample a voltage stored in at least one of the plurality of capacitors in a case where the plurality of switchable resistors have been controlled to connect the plurality of capacitors and a time period has elapsed; and

said one or more circuits configured to update the exposure information based on said voltage.

22. The image sensor circuit of claim 1,

said plurality of pixel circuits arranged in a plurality of rows and a plurality of columns, each of the plurality of rows further including a threshold current generator;

said one or more circuits configured to compare a voltage of a reference signal derived from an output of a particular threshold current generator in a particular row of the plurality of rows with a voltage of a signal derived from an output of a particular pixel circuit of the plurality of pixel circuits that is in the particular row, and configured to update the exposure information based on a result of the comparison.

23. The image sensor circuit of claim 1,

said one or more circuits configured to terminate an image capture operation in the pixel array based on a comparison between a threshold number and a number calculated from the exposure information.

24. The image sensor circuit of claim 1,

said one or more circuits comprising a digital signal processor.

25. The image sensor circuit of claim 1, further comprising:

an infrared filter located on at least a portion of at least one pixel circuit of the plurality of pixel circuits.

26. The image sensor circuit of claim 1, further comprising:

a color filter located on at least a portion of at least one pixel circuit of the plurality of pixel circuits.

27. A method in an image sensor circuit, the image sensor circuit including a pixel array having a plurality of pixel circuits, the method comprising:

storing information related to an exposure pattern of the pixel array; and

changing the exposure pattern of the pixel array based at least partially on (i) the information that has been stored and (ii) one or more signals output from the pixel array, wherein said one or more signals output from the pixel array is nondestructive with respect to charge accumulating at a sense node of at least one of the plurality of pixel circuits.

28. A method in an image sensor circuit, the image sensor circuit including a pixel array having a plurality of pixel circuits, the method comprising:

starting an integration of charge in each of the plurality of pixel circuits;

preventing the integration of charge in at least a particular pixel circuit of the plurality of pixel circuits that is selected based at least partially on one or more signals output from the pixel array, wherein said one or more signals output from the pixel array is nondestructive with respect to charge accumulating at a sense node of at least one of the plurality of pixel circuits; and

preventing the integration of charge in at least one pixel circuit of the plurality of pixel circuits that is adjacent to the particular pixel circuit in the pixel array based at least partially on a dilation rule.

29. A pixel circuit, comprising:

a photodiode;

a first transistor connected between the photodiode and a sense node, wherein a voltage of the sense node controls an output signal having a readout that is nondestructive with respect to charge accumulating at the sense node; and

a second transistor connected between an exposure control signal line and a gate of the first transistor, the second transistor having a gate connected to a transfer signal line.

30. An image processing system, comprising:

an image sensor circuit comprising a pixel array and configured to obtain an image using a type of shutter operation in which an exposure pattern of the pixel array is set according to exposure information that changes over time based at least partially on charge accumulated in at least a portion of the pixel array, wherein a readout of the at least a portion of the pixel array is nondestructive with respect to charge accumulating at the at least a portion of the pixel array; and

a processor configured to detect one or more objects in the image.