Semiconductor device with dummy pattern within active region and method of manufacturing the same

• US 8,063,412 B2
• Filed: 11/11/2008
• Issued: 11/22/2011
• Est. Priority Date: 11/15/2007
• Status: Active Grant

• Current Assignee: Sony Corporation (Sony Group Corp.)
• Original Assignee: Sony Corporation (Sony Group Corp.)
• Inventors: Tsuno, Hitoshi
• Primary Examiner(s): Pham; Hoai V
• Application Number:
  US12/268,506
• Publication Number:
  US 20090127634A1
• Time in Patent Office: 1,106 Days
• Field of Search: 257/173, 257/202, 257/337, 257/338, 257/355, 257/368, 257/369, 257/E29.014
• US Class Current: 257/173
• CPC Class Codes: H01L 21/823437 with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
• CPC Class Codes: H01L 27/0207 Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
• CPC Class Codes: H01L 29/7843 the means being an applied insulating layer
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A semiconductor device includes a semiconductor substrate having an active region, a plurality of gate electrodes formed on the active region with a gate insulating film therebetween, and a dummy pattern formed on the active region in at least a part thereof between the gate electrodes. The dummy pattern is formed so that a spacing between gate electrodes adjacent to each other, and a spacing between the dummy pattern and the gate electrodes adjacent to the dummy pattern, are within predetermined ranges.

Claims

1. A semiconductor device comprising:

a semiconductor substrate having an active region and an isolation region;

at least first, second and third gate electrodes on the substrate within the active region with a gate insulating film interposed therebetween; and

a dummy pattern formed within the active region in at least a part thereof between the second and third gate electrodes,

wherein,

the distance between the first and second gate electrodes is D1,

the distance between the second and third gate electrodes is D2,

the distance between the second gate electrode and the dummy electrode is d1,

the distance between the dummy electrode and the third gate electrode is d2

the distance between the isolation region and the first gate electrode is d3,

the distance between the third gate electrode and the isolation region is d4,

D1 is not equal to D2,

d2 is equal to D1 plus a tolerance value, and

when D1 is not equal to d3 or D1 is not equal to d4, then d3 is equal to D1 plus the tolerance value, but d4 is not equal to d3.

2. The semiconductor device as claimed in claim 1, wherein the dummy pattern is composed in part of a sidewall forming film used for forming sidewalls on side faces of the gate electrodes.

3. The semiconductor device as claimed in claim 1, further comprising a stress liner film cover the gate electrodes and the dummy pattern which applies a stress to the semiconductor substrate.

4. The semiconductor device as claimed in claim 1, comprising diffusion layers formed in the semiconductor substrate at both sides of the dummy pattern and which are connected to each other via an interconnect.

5. The semiconductor device as claimed in claim 1, wherein the dummy pattern has a slit as deep as reaching the semiconductor substrate.

6. The semiconductor device as claimed in claim 1, wherein the dummy pattern is composed of an insulating film different from the sidewall forming film on the gate electrodes.