Semiconductor device having reduced thickness, electronic product employing the same, and methods of fabricating the same

• US 8,063,425 B2
• Filed: 09/18/2008
• Issued: 11/22/2011
• Est. Priority Date: 09/18/2007
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Kim, Yong-Il, Kim, Dae-Ik
• Primary Examiner(s): Sefer; A.
• Assistant Examiner(s): Harrison; Monica D
• Application Number:
  US12/232,498
• Publication Number:
  US 20090072289A1
• Time in Patent Office: 1,160 Days
• Field of Search: 257/298, 257/E29.345, 257/368, 438/241
• US Class Current: 257/298
• CPC Class Codes: H01L 21/82345 gate conductors with different gate conductor materials or different gate conductor implants, e.g. dual gate structures
• CPC Class Codes: H01L 21/823456 gate conductors with different shapes, lengths or dimensions
• CPC Class Codes: H01L 21/823462 with a particular manufacturing method of the gate insulating layers, e.g. different gate insulating layer thicknesses, particular gate insulator materials or particular gate insulator implants
• CPC Class Codes: H01L 27/088 the components being field-effect transistors with insulated gate
• CPC Class Codes: H01L 27/105 including field-effect components
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/66621 using etching to form a recess at the gate location etching of semiconductor bodies H01L21/302
• CPC Class Codes: H10B 12/053 the transistor being at least partially in a trench in the substrate vertical transistor in combination with a capacitor formed in a substrate trench H10B12/0383
• CPC Class Codes: H10B 12/09 with simultaneous manufacture of the peripheral circuit region and memory cells
• CPC Class Codes: H10B 99/00 Subject matter not provided for in other groups of this subclass

Abstract

A semiconductor device capable of reducing a thickness, an electronic product employing the same, and a method of fabricating the same are provided. The method of fabricating a semiconductor device includes preparing a semiconductor substrate having first and second active regions. A first transistor in the first active region includes a first gate pattern and first impurity regions. A second transistor the second active region includes a second gate pattern and second impurity regions. A first conductive pattern is on the first transistor, wherein at least a part of the first conductive pattern is disposed at a same distance from an upper surface of the semiconductor substrate as at least a part of the second gate pattern. The first conductive pattern may be formed on the first transistor while the second transistor is formed.

Claims

1. A semiconductor device, comprising:

a semiconductor substrate having a first circuit region and a second circuit region, the semiconductor substrate including an isolation region to define a first active region and a second active region in the first circuit region and the second circuit region, respectively;

a first transistor in the first active region of the semiconductor substrate, the first transistor including first impurity regions and a first gate pattern;

an insulating pattern on the first transistor and the isolation region of the first circuit region;

a second transistor in the second active region of the second circuit region, the second transistor including second impurity regions and a second gate pattern; and

a first conductive pattern formed on the insulating pattern, wherein at least a part of the first conductive pattern is disposed at a same distance from an upper surface of the semiconductor substrate as at least a part of the second gate pattern,

wherein a bottom surface of the second gate pattern is disposed at a lower level than an interface between the first conductive pattern and the insulating pattern.

2. The device as claimed in claim 1, wherein the first transistor includes:

the first gate pattern provided in a gate trench crossing the first active region;

the first impurity regions in the first active region at both sides of the first gate pattern; and

a first gate dielectric layer provided between the first gate pattern and the gate trench.

3. The device as claimed in claim 2, further comprising an insulating first gate capping pattern filling the gate trench together with the first gate pattern.

4. The device as claimed in claim 1, further comprising a first contact structure configured to pass through the insulating pattern and electrically connect one of the first impurity regions, wherein the first contact structure is electrically connected to the first conductive pattern.

5. The device as claimed in claim 1, wherein the second transistor includes:

the second gate pattern crossing the second active region;

a second gate dielectric layer provided between the second gate pattern and the active region; and

second impurity regions in the second active region at both sides of the second gate pattern,

wherein the second gate pattern includes a first gate electrode and a second gate electrode, which are sequentially stacked, and the second gate electrode is disposed at substantially a same height above the upper surface of the semiconductor substrate as the first conductive pattern.

6. The device as claimed in claim 1, further comprising:

a cell contact structure electrically connected to one of the first impurity regions; and

a data storage element on the cell contact structure.

7. The device as claimed in claim 6, wherein the data storage element is disposed at a higher level than the first conductive pattern.

8. The device as claimed in claim 6, further comprising a conductive buffer pattern provided between the cell contact structure and the data storage element.

9. The device as claimed in claim 6, wherein the data storage element includes one of a data storage material layer of a volatile memory device and a data storage material layer of a non-volatile memory device.

10. The device as claimed in claim 6, further comprising:

a second conductive pattern disposed at a higher level than the first conductive pattern; and

a second contact structure configured to electrically connect one of the second impurity regions to the second conductive pattern.

11. The device as claimed in claim 10, wherein the cell contact structure and the second contact structure have upper surfaces disposed at different levels from each other.

12. The device as claimed in claim 10, wherein the cell contact structure and the second contact structure have upper surfaces disposed at the substantially same level.

13. The device as claimed in claim 10, further comprising a connection structure configured to electrically connect the first and second conductive patterns.

27. The device as claimed in claim 1, wherein the second gate pattern has a thickness greater than a thickness of the first conductive pattern.

28. The device as claimed in claim 1, wherein the first gate pattern is disposed at a different level from the second gate pattern.

29. The device as claimed in claim 1, wherein an upper surface of the second gate pattern is disposed at substantially a same height above the upper surface of the semiconductor substrate as an upper surface of the first conductive pattern.

30. The device as claimed in claim 2, wherein the first gate pattern is configured to partially fill the gate trench that runs across the first active region between the first impurity regions and extends to the isolation region of the first circuit region.

31. The device as claimed in claim 3, wherein a part of the insulating pattern is disposed between the first gate capping pattern and the first conductive pattern.

32. The device as claimed in claim 3, wherein the first gate capping pattern has a projection further from the upper surface of the semiconductor substrate than the first active region.

33. The device as claimed in claim 32, wherein the first gate capping pattern is configured to pass through the insulating pattern.

14. An electronic product comprising a semiconductor chip, the semiconductor chip comprising:

a semiconductor substrate having a cell array region and a peripheral circuit region;

a cell transistor on the semiconductor substrate of the cell array region, a first gate dielectric layer, the cell transistor including first impurity regions and a first gate pattern;

a peripheral transistor on the semiconductor substrate of the peripheral circuit region, the peripheral transistor including second impurity regions, a second gate dielectric layer and a second gate pattern, wherein the second gate pattern includes a first peripheral gate electrode and a second peripheral gate electrode, which are sequentially stacked on the substrate between the second impurity regions;

an insulating pattern on the first transistor of the cell array region;

a cell conductive pattern on the cell transistor of the cell array region, the cell conductive pattern having at least a part disposed at a same distance from an upper surface of the semiconductor substrate as at least a part of the second peripheral gate electrode; and

a cell contact structure formed to pass through the insulating pattern and electrically connected one of the first impurity regions, wherein the cell contact structure is electrically connected to the cell conductive pattern,

wherein a bottom surface of the second gate pattern is disposed at a lower level than an interface between the cell conductive pattern and the insulating pattern.

15. A method of fabricating a semiconductor device, comprising:

preparing a semiconductor substrate having first and second active regions;

forming a first transistor in the first active region, the first transistor including a first gate pattern and first impurity regions;

forming a buffer isolation pattern on the first active region;

forming a second transistor in the second active region, the second transistor including a second gate pattern and second impurity; and

forming a first conductive pattern on the buffer insulating pattern, wherein at least a part of the first conductive pattern is disposed at a same distance from an upper surface of the semiconductor substrate as at least a part of the second gate pattern,

wherein a bottom surface of the second gate pattern is disposed at a lower level than an interface between the conductive pattern and the buffer insulating pattern.

16. The method as claimed in claim 15, wherein forming the first and second transistors and the first conductive pattern includes:

forming the first impurity regions in the first active region;

forming a gate trench crossing the first active region;

forming the first gate pattern filling at least a part of the gate trench;

forming a gate conductive pattern on the second active region;

forming the buffer insulating pattern on the first active region;

forming a first conductive layer covering the buffer insulating pattern and the gate conductive pattern; and

patterning the first conductive layer on the buffer insulating pattern, and the gate conductive pattern and the first conductive layer, which are sequentially stacked on the second active region, so that the first conductive pattern is formed on the buffer insulating pattern, and a first gate electrode and a second gate electrode, which are sequentially stacked, is formed on the second active region.

17. The method as claimed in claim 16, after forming the first gate pattern, further comprising forming a first gate capping pattern to fill the gate trench together with the first gate pattern on the first gate pattern,

wherein the first gate capping pattern extends further above the upper surface of the semiconductor substrate than the first active region.

18. The method as claimed in claim 16, wherein forming the buffer insulating pattern occurs after forming the gate conductive pattern.

19. The method as claimed in claim 16, wherein forming the gate conductive pattern occurs after forming the buffer insulating pattern.

20. The method as claimed in claim 16, before forming the first conductive pattern, further comprising forming a first contact structure configured to pass through the buffer insulating pattern, and electrically connected to one of the first impurity regions,

wherein the first conductive structure is electrically connected to the first conductive pattern.

21. The method as claimed in claim 15, further comprising:

forming a first interlayer insulating layer on the substrate having the first conductive pattern;

forming a cell contact structure configured to pass through the first interlayer insulating layer and electrically connected to one of the first impurity regions; and

forming a data storage element on the cell contact structure.

22. The method as claimed in claim 21, further comprising:

while forming the cell contact structure, forming a peripheral contact structure configured to pass through the first interlayer insulating layer and electrically connected to one of the second impurity regions; and

forming a second conductive pattern electrically connected to the peripheral contact structure on the first interlayer insulating layer.

23. The method as claimed in claim 22, further comprising, while forming the second conductive pattern, forming a buffer pattern electrically connected to the cell contact structure on the first interlayer insulating layer.

24. The method as claimed in claim 21, further comprising:

forming a second interlayer insulating layer on the first interlayer insulating layer;

forming a second contact structure configured to pass through the first and second interlayer insulating layers, and electrically connected to one of the second impurity regions; and

forming a second conductive pattern on the second interlayer insulating layer.

25. The method as claimed in claim 15, wherein forming the first conductive pattern occurs while forming the second gate pattern.

26. A method of fabricating a semiconductor device, comprising:

preparing a semiconductor substrate having first and second regions;

forming an insulating pattern on the semiconductor substrate of the first region;

forming a conductive pattern on the semiconductor substrate of the second region;

forming a conductive layer covering the conductive pattern and the insulating pattern; and

patterning the conductive layer and the conductive pattern, forming an interconnection on the insulating pattern, and forming a first gate electrode and a second gate electrode, which are sequentially stacked on the semiconductor substrate of the second region.

34. A semiconductor device, comprising:

a semiconductor substrate having a first circuit region and a second circuit region;

an insulating pattern on the semiconductor substrate of the first circuit region;

a conductive pattern on the semiconductor substrate of the second circuit region and

a transistor in the semiconductor substrate of the second circuit region, the transistor including impurity regions and a gate pattern, wherein the gate pattern includes a first gate electrode and a second gate electrode, which are sequentially stacked,

wherein the insulating pattern is disposed at substantially the same level as the first gate electrode,

wherein the conductive pattern is disposed at substantially the same level as the second gate electrode.

35. The device as claimed in claim 34, further comprising a cell transistor in the first circuit region of the semiconductor substrate,

wherein the cell transistor includes cell impurity regions and a cell gate electrode,

wherein the cell gate electrode is disposed at a different level from the gate pattern.

36. The device as claimed in claim 34, wherein the conductive pattern and the second gate electrode is formed of the same conductive material.