Fast switching power insulated gate semiconductor device
First Claim
1. An insulated gate device comprising a source connected to a source terminal, a gate connected to a gate terminal and input capacitance means providing capacitance between the gate terminal and the source terminal, wherein a value of the capacitance is a function of an effective thickness of an insulation layer at the gate, the effective thickness of the insulation layer being selected to ensure that a first ratio (Cfiss/Ciiss) between a final value (Cfiss) of the capacitance when the device is on and an initial value (Ciiss) of the capacitance when the device is off is smaller or equal to a second ratio (QG(max)/QG(min)) of a maximum allowable gate charge (QG(max)) and a minimum charge (QG(min)) required on the gate for complete switching of the device and such that 1<
- Cfiss/Ciiss<
2.0.
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Accused Products
Abstract
An insulated gate semiconductor device (30) includes a gate (34), a source terminal (36), a drain terminal (38) and a variable input capacitance at the gate. A ratio between the input capacitance (Cfiss) when the device is on and the input capacitance Ciiss when the device is off is less than two and preferably substantially equal to one. This is achieved in one embodiment of the invention by an insulation layer 32 at the gate having an effective thickness dins larger than a minimum thickness.
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Citations
18 Claims
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1. An insulated gate device comprising a source connected to a source terminal, a gate connected to a gate terminal and input capacitance means providing capacitance between the gate terminal and the source terminal, wherein a value of the capacitance is a function of an effective thickness of an insulation layer at the gate, the effective thickness of the insulation layer being selected to ensure that a first ratio (Cfiss/Ciiss) between a final value (Cfiss) of the capacitance when the device is on and an initial value (Ciiss) of the capacitance when the device is off is smaller or equal to a second ratio (QG(max)/QG(min)) of a maximum allowable gate charge (QG(max)) and a minimum charge (QG(min)) required on the gate for complete switching of the device and such that 1<
- Cfiss/Ciiss<
2.0. - View Dependent Claims (2, 3, 4, 5, 6)
- Cfiss/Ciiss<
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7. An insulated gate device comprising a source connected to a source terminal, a gate connected to a gate terminal and input capacitance means providing capacitance between the gate terminal and the source terminal, wherein a value of the capacitance is a function of an effective thickness of an insulation layer at the gate, the effective thickness of the insulation layer being selected to ensure that a first ratio (Cfiss/Ciiss) between a final value (Cfiss) of the capacitance when the device is on and an initial value (Ciiss) of the capacitance when the device is off is smaller or equal to a second ratio (VGS(max)/VGS(min)) of a maximum allowable gate voltage (VGS(max)) and a minimum gate voltage (VGS(min)) for complete switching of the device and such that 1<
- Cfiss/Ciiss<
2.0. - View Dependent Claims (8, 9, 10, 11, 12)
- Cfiss/Ciiss<
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13. An insulated gate device comprising a gate and an insulation layer at the gate, the insulation layer having an effective thickness (d) of at least a quotient of a device parameter (β
- ) and a ratio of maximum allowable gate charge (QG(max)) and a minimum charge (QG(min)) required on the gate for complete switching, minus one (1), d ≧
β
/[(QG(max)/QG(min))−
1], the device parameter (β
) being equal to the product of an effective gate capacitance area (A) and a difference between an inverse of a first value (1/Ciiss) of a gate capacitance of the insulated gate device, that is when the device is off and an inverse of a second value (1/Cfiss) of the gate capacitance, that is when the insulated gate device is on, β
=A(1/Ciiss−
1/Cfiss) and such that 1<
Cfiss/Ciiss<
2.0. - View Dependent Claims (14, 15, 16, 17, 18)
- ) and a ratio of maximum allowable gate charge (QG(max)) and a minimum charge (QG(min)) required on the gate for complete switching, minus one (1), d ≧
Specification