Fast switching power insulated gate semiconductor device

• US 8,063,426 B2
• Filed: 01/28/2008
• Issued: 11/22/2011
• Est. Priority Date: 01/21/2003
• Status: Expired due to Fees

• Current Assignee: Ambixtra (Pty) Ltd.
• Original Assignee: Northwest University
• Inventors: De Jager, Ocker Cornelis, Visser, Barend
• Primary Examiner(s): Loke; Steven
• Assistant Examiner(s): GOODWIN, DAVID J
• Application Number:
  US12/021,037
• Publication Number:
  US 20080203457A1
• Time in Patent Office: 1,394 Days
• Field of Search: 257/340, 257/331.E21419 E23019
• US Class Current: 257/312
• CPC Class Codes: H01L 25/07 the devices being of a type provided for in group H01L29/00
• CPC Class Codes: H01L 29/42364 characterised by the insulating layer, e.g. thickness or uniformity H01L29/42324 and H01L29/4234 take precedence
• CPC Class Codes: H01L 29/7802 Vertical DMOS transistors, i.e. VDMOS transistors
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H03K 17/04123 in field-effect transistor switches

Abstract

An insulated gate semiconductor device (30) includes a gate (34), a source terminal (36), a drain terminal (38) and a variable input capacitance at the gate. A ratio between the input capacitance (C_fiss) when the device is on and the input capacitance C_iiss when the device is off is less than two and preferably substantially equal to one. This is achieved in one embodiment of the invention by an insulation layer 32 at the gate having an effective thickness d_ins larger than a minimum thickness.

Claims

1. An insulated gate device comprising a source connected to a source terminal, a gate connected to a gate terminal and input capacitance means providing capacitance between the gate terminal and the source terminal, wherein a value of the capacitance is a function of an effective thickness of an insulation layer at the gate, the effective thickness of the insulation layer being selected to ensure that a first ratio (C_fiss/C_iiss) between a final value (C_fiss) of the capacitance when the device is on and an initial value (C_iiss) of the capacitance when the device is off is smaller or equal to a second ratio (Q_G(max)/Q_G(min)) of a maximum allowable gate charge (Q_G(max)) and a minimum charge (Q_G(min)) required on the gate for complete switching of the device and such that 1<

C_fiss/C_iiss<

2.0.

2. A device as claimed in claim 1 comprising a power metal oxide silicon field effect transistor (MOSFET).

3. A device as claimed in claim 1 wherein said input capacitance means provides input capacitance such that the ratio (C_fiss/C_iiss) is 1<

C_fiss/C_iiss<

1.5.

4. A device as claimed in claim 3 wherein said input capacitance means provides input capacitance such that the ratio (C_fiss/C_iiss) is 1<

C_fiss/C_iiss<

1.2.

5. A device as claimed in claim 2 wherein the MOSFET has a vertical structure in that the gate and the source of the device are provided on one face of a chip body of the device and a drain of the MOSFET is provided on an opposite face of the chip body, wherein said input capacitance means comprises a series capacitor between the gate terminal and the gate of the device.

6. A device as claimed in claim 1 wherein the gate is connected directly to an additional terminal of the device.

7. An insulated gate device comprising a source connected to a source terminal, a gate connected to a gate terminal and input capacitance means providing capacitance between the gate terminal and the source terminal, wherein a value of the capacitance is a function of an effective thickness of an insulation layer at the gate, the effective thickness of the insulation layer being selected to ensure that a first ratio (C_fiss/C_iiss) between a final value (C_fiss) of the capacitance when the device is on and an initial value (C_iiss) of the capacitance when the device is off is smaller or equal to a second ratio (V_GS(max)/V_GS(min)) of a maximum allowable gate voltage (V_GS(max)) and a minimum gate voltage (V_GS(min)) for complete switching of the device and such that 1<

C_fiss/C_iiss<

2.0.

8. A device as claimed in claim 7, comprising a power metal oxide silicon field effect transistor (MOSFET).

9. A device as claimed in claim 8, wherein the MOSFET has a vertical structure in that the gate and the source of the device are provided on one face of a chip body of the device and a drain of the MOSFET is provided on an opposite face of the chip body, wherein said input capacitance means comprises a capacitor between the gate terminal and the gate of the device.

10. A device as claimed in claim 7, wherein said input capacitance means provides input capacitance such that the ratio (C_fiss/C_iiss) is 1<

C_fiss/C_iiss<

1.5.

11. A device as claimed in claim 10, wherein said input capacitance means provides input capacitance such that the ratio (C_fiss/C_iiss) is 1<

C_fiss/C_iiss<

1.2.

12. A device as claimed in claim 7, wherein the gate is connected directly to an additional terminal of the device.

13. An insulated gate device comprising a gate and an insulation layer at the gate, the insulation layer having an effective thickness (d) of at least a quotient of a device parameter (β

) and a ratio of maximum allowable gate charge (Q_G(max)) and a minimum charge (Q_G(min)) required on the gate for complete switching, minus one (1), d ≧

β

/[(Q_G(max)/Q_G(min))−

1], the device parameter (β

) being equal to the product of an effective gate capacitance area (A) and a difference between an inverse of a first value (1/C_iiss) of a gate capacitance of the insulated gate device, that is when the device is off and an inverse of a second value (1/C_fiss) of the gate capacitance, that is when the insulated gate device is on, β

=A(1/C_iiss−

1/C_fiss) and such that 1<

C_fiss/C_iiss<

2.0.

14. A device as claimed in claim 13, comprising a power metal oxide silicon field effect transistor (MOSFET).

15. A device as claimed in claim 14, wherein the MOSFET has a vertical structure in that the gate and a source of the device are provided on one face of a chip body of the device and a drain of the MOSFET is provided on an opposite face of the chip body, and further comprising a gate terminal and a series capacitor between the gate terminal and the gate of the device.

16. A device as claimed in claim 13, wherein the ratio (C_fiss/C_iiss) is 1<

C_fiss/C_iiss<

1.5.

17. A device as claimed in claim 16, wherein the ratio (C_fiss/C_iiss) is 1<

C_fiss/C_iiss<

1.2.

18. A device as claimed in claim 13, wherein the gate is connected directly to an additional terminal of the device.