On-chip temperature gradient minimization using carbon nanotube cooling structures with variable cooling capacity

• US 8,063,483 B2
• Filed: 10/18/2007
• Issued: 11/22/2011
• Est. Priority Date: 10/18/2007
• Status: Expired due to Fees

• Current Assignee: GlobalFoundries, Inc.
• Original Assignee: International Business Machines Corporation
• Inventors: Dimitrakopoulos, Christo Dimitrios, Grill, Alfred, Georgiou, Christos John, Rogowitz, Bernice E.
• Primary Examiner(s): Vu; Hung
• Application Number:
  US11/874,861
• Publication Number:
  US 20090102046A1
• Time in Patent Office: 1,496 Days
• Field of Search: 257/706, 257/707, 257/712, 257/717, 257/720, 257/E21.001, 257/E23.08, 977/842, 977/932
• US Class Current: 257/712
• CPC Class Codes: H01L 23/373 Cooling facilitated by selection of materials for the device or materials for thermal expansion adaptation, e.g. carbon
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

An electronic device comprises a die with at least one defined hot-spot area; and at least one defined intermediate temperature area at a temperature lower than the temperature of the hot-spot area. The device also comprises a cooling structure comprising at least one bundle of first nanotubes for cooling the hot spot area and at least one bundle of additional nanotubes for cooling the intermediate temperature area, and having heat conductivity lower than the bundle of first nanotubes. The heat conductivity of both sets of the nanotubes is sufficient to decrease any temperature gradient between the defined hot spot area, the defined intermediate temperature area, and at least one lower temperature area on the die. The walls of the first nanotubes and the additional nanotubes are surrounded by a heat conducting matrix material operatively associated with the lower temperature area.

Claims

1. A semiconductive device comprising a die wherein the die comprises:

(a) at least one defined hot-spot area lying in a plane on the die;

(b) at least one defined minimum temperature area comprising an area lying in the plane on said die and at a temperature lower than the temperature of said hot-spot area, wherein said minimum temperature area comprises the minimum temperature of said die;

(c) at least one defined intermediate temperature area comprising an area lying in the plane on said die at a temperature intermediate the temperature of said hot-spot area and said minimum temperature area;

(d) cooling means comprising at least one bundle of first nanotube means composed of a heat conducting material and extending in a direction outwardly from the plane of said hot-spot area, said first nanotube means being operatively associated with and in heat conducting relationship with said hot-spot area and having heat conductivity sufficient to decrease any temperature gradient between said hot-spot area and any other temperature areas on the die;

(e) cooling means comprising at least one bundle of additional nanotube means composed of a heat conducting material and extending in a direction outwardly from the plane of said intermediate temperature area, said additional nanotube means being operatively associated with and in heat conducting relationship with said intermediate temperature area and having heat conductivity sufficient to decrease any temperature gradient between said the intermediate temperature area and any other temperature areas on the die;

(f) the heat conductivity of said bundle of first nanotube means being greater than the heat conductivity of said additional nanotube means;

(g) said bundle of first nanotube means and said bundle of additional nanotube means being substantially surrounded by a matrix material comprised of a heat conducting material operatively associated with and in heat conducting relation with said minimum temperature area;

(h) the heat conductivity of said bundle of first nanotube means and said bundle of additional nanotube means being greater than the heat conductivity of said matrix material;

(i) the distal ends of said bundle of first nanotube means and said bundle of additional nanotube means being positioned for direct contact with a medium comprising a heat exchange medium.

2. The device of claim 1 comprising said bundle of first nanotube means, said bundle of additional nanotube means and said matrix material wherein said bundle of first nanotube means are substantially parallel to one another;

and said bundle of additional nanotube means are substantially parallel to one another; and

said bundle of first nanotube means and said bundle of additional nanotube means substantially;

(a) are linear or helical;

(b) are perpendicular to the plane of said hot spot;

(c) comprise single wall or multi-wall nanotubes.

3. The device of claim 2 wherein said bundle of first nanotube means and said bundle of additional nanotube means have different arial densities on said device wherein said nanotube means having the higher arial density on said device cools the device at a rate higher than said nanotube means with the lower arial density on said device.

4. The device of claim 2 wherein said nanotubes in the said bundle of first nanotube means and said nanotubes in the bundle of additional nanotube means have different diameters wherein the said nanotube means having smaller diameter nanotubes cools said device at a rate higher than said nanotube means with larger diameter nanotubes.

5. The device of claim 2 wherein said matrix material comprises a metal material and said nanotube means comprises carbon.

6. The device of claim 2 comprising a VLSI device.