Semiconductor device assemblies and packages

• US 8,063,493 B2
• Filed: 11/30/2009
• Issued: 11/22/2011
• Est. Priority Date: 09/30/2003
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Boon, Suan Jeung, Low, Siu Waf, Chia, Yong Poo, Eng, Meow Koon
• Primary Examiner(s): CHU, CHRIS C
• Application Number:
  US12/627,352
• Publication Number:
  US 20100072603A1
• Time in Patent Office: 722 Days
• Field of Search: 257/E25.013, 257/E25.018, 257/E23.068, 257/685, 257/686, 257/690, 257/723, 257/730, 257/773, 257/777, 438/108, 438/109, 361/760
• US Class Current: 257/777
• CPC Class Codes: H01L 21/4846 Leads on or in insulating or insulated substrates, e.g. metallisation H01L21/4821 takes precedence; metallisation of ceramics in general C04B41/51; printed circuits H05K3/00
• CPC Class Codes: H01L 21/568 Temporary substrate used as encapsulation process aid H01L21/4832 and H01L21/566 take precedence
• CPC Class Codes: H01L 21/6835 using temporarily an auxiliary support
• CPC Class Codes: H01L 2225/1058 Bump or bump-like electrical connections, e.g. balls, pillars, posts
• CPC Class Codes: H01L 23/3114 the device being a chip scale package, e.g. CSP
• CPC Class Codes: H01L 23/3121 a substrate forming part of the encapsulation
• CPC Class Codes: H01L 23/49805 the leads being also applied on the sidewalls or the bottom of the substrate, e.g. leadless packages for surface mounting
• CPC Class Codes: H01L 23/49816 Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
• CPC Class Codes: H01L 24/97 the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 25/105 the devices being of a type provided for in group H01L27/00
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/01033 Arsenic [As]
• CPC Class Codes: H01L 2924/01049 Indium [In]
• CPC Class Codes: H01L 2924/01075 Rhenium [Re]
• CPC Class Codes: H01L 2924/01078 Platinum [Pt]
• CPC Class Codes: H01L 2924/09701 Low temperature co-fired ceramic [LTCC]
• CPC Class Codes: H01L 2924/12041 LED
• CPC Class Codes: H01L 2924/12042 LASER
• CPC Class Codes: H01L 2924/3025 Electromagnetic shielding
• CPC Class Codes: H01L 2924/351 Thermal stress

Abstract

A sacrificial substrate for fabricating semiconductor device assemblies and packages with edge contacts includes conductive elements on a surface thereof, which are located so as to align along a street between each adjacent pair of semiconductor devices on the device substrate. A semiconductor device assembly or package includes a semiconductor device, a redistribution layer over an active surface of the semiconductor device, and dielectric material coating at least portions of an outer periphery of the semiconductor device. Peripheral sections of contacts are located on the peripheral edge and electrically isolated therefrom by the dielectric coating. The contacts may also include upper sections that extend partially over the active surface of the semiconductor device. The assembly or package may include any type of semiconductor device, including a processor, a memory device, and emitter, or an optically sensitive device.

Claims

1. A semiconductor device assembly, comprising:

an electronic device component having a chip-bearing surface carrying a plurality of contacts;

a chip-scale package positioned over the chip-bearing surface of the electronic device component, the chip-scale package including;

a semiconductor device; and

a plurality of contacts substantially corresponding to the plurality of contacts of the electronic device component, each chip-scale package contact of the plurality of contacts including;

an upper element extending over a portion of an active surface of the semiconductor device of the chip-scale package;

a peripheral element extending from at least an active surface of the semiconductor device over a portion of a lateral periphery of the semiconductor device to at least a back side of the semiconductor device; and

a bottom element extending over a portion of the back side of the semiconductor device;

wherein the upper element and the bottom element are in contact with the peripheral element and a peripheral end of at least one of the upper element and the bottom element forms a discernable boundary with an inner surface of the peripheral element; and

intermediate conductive elements operably coupled between and in direct contact with at least some contacts of the plurality of contacts of the electronic device component and at least the bottom element of corresponding chip-scale package contacts.

2. The semiconductor device assembly of claim 1, wherein the back side of the semiconductor device of the chip-scale package is spaced apart from the chip-bearing surface of the electronic device component by the intermediate conductive elements.

3. The semiconductor device assembly of claim 1, wherein each intermediate conductive element is also operably coupled to the peripheral element of a corresponding chip-scale package contact by direct contact with the intermediate conductive element.

4. The semiconductor device assembly of claim 3, wherein each intermediate conductive element of the intermediate conductive elements comprises a metal material.

5. The semiconductor device assembly of claim 4, wherein each intermediate conductive element of the intermediate conductive elements comprises solder.

6. The semiconductor device assembly of claim 1, further comprising:

another chip-scale package oriented at least partially over the active surface of the chip-scale package, the another chip-scale package including;

a semiconductor device; and

a plurality of contacts corresponding to the plurality of contacts of the chip-scale package, each chip-scale package contact of the plurality of contacts of the another chip-scale package including;

a bottom element extending over a portion of a back side of the semiconductor device; and

intermediate conductive elements operably coupled between the upper element of at least some chip-scale package contacts of the chip-scale package and at least the bottom element of a corresponding chip-scale package contact of the another chip-scale package.

7. The semiconductor device assembly of claim 1, wherein the electronic device component comprises a redistribution carrier.

8. The semiconductor device assembly of claim 7, wherein the redistribution carrier includes a back side opposite the chip-bearing surface.

9. The semiconductor device assembly of claim 8, further comprising:

a carrier substrate; and

intermediate conductive elements electrically coupling terminals of the carrier substrate to corresponding terminals of the redistribution carrier.

10. The semiconductor device assembly of claim 9, wherein the redistribution carrier is superimposed over at least a portion of the carrier substrate, terminals of the redistribution carrier are substantially aligned with corresponding terminals of the carrier substrate, and the intermediate conductive elements are disposed between substantially aligned pairs of corresponding terminals of the redistribution element and the carrier substrate.

11. The semiconductor device assembly of claim 1, wherein the chip-scale package further includes:

a redistribution layer over an active surface of the semiconductor device extending between bond pads of the semiconductor device and upper elements of contacts of the plurality of contacts;

a peripheral dielectric coating covering at least a portion of an outer lateral periphery of the semiconductor device, the peripheral dielectric coating including an edge adjacent to a junction between a lateral periphery and a back side of the semiconductor device;

a back side dielectric coating on at least a portion of the back side of the semiconductor device and including a peripheral edge abutting and forming a discernable boundary with a major surface of the peripheral dielectric coating;

the peripheral element of each chip-scale package contact being carried by the peripheral dielectric coating, spaced apart from the back side dielectric coating by the peripheral dielectric coating, and including an end adjacent to the edge of the peripheral dielectric coating; and

the bottom element of each chip-scale package contact being carried partially by the back side dielectric coating, the edge of the peripheral dielectric coating and the end of the peripheral element abutting and forming a discernable boundary with a peripheral edge of the bottom element.

12. The semiconductor device assembly of claim 1, wherein the chip-scale package further includes:

a redistribution layer over an active surface of the semiconductor device extending from bond pads of the semiconductor device to upper elements of contacts of the plurality of contacts of the semiconductor device; and

a peripheral dielectric coating covering at least a portion of an outer lateral periphery of the semiconductor device between the active surface and back side of the semiconductor device under the peripheral elements of the plurality of contacts of the semiconductor device;

a back side dielectric coating on at least a portion of the back side of the semiconductor device and including a peripheral edge abutting and forming a discernable boundary with the peripheral dielectric coating; and

the bottom element of each chip-scale package contact extending over a portion of the back side dielectric coating.

13. A semiconductor device assembly, comprising an electronic device component having a chip-scale package mounted thereto, the chip-scale package including:

a semiconductor device; and

a plurality of contacts, each chip-scale package contact of the plurality of contacts including;

an upper element extending over a portion of an active surface of the semiconductor device of the chip-scale package;

a peripheral element extending from a location at least adjacent an active surface of the semiconductor device over a portion of a lateral periphery of the semiconductor device to a location at least adjacent a back side of the semiconductor device; and

a bottom element extending over a portion of the back side of the semiconductor device;

wherein the upper element and the bottom element are in contact with the peripheral element and a peripheral end of at least one of the upper element and the bottom element forms a discernable boundary with an inner surface of the peripheral element.

14. The semiconductor device assembly of claim 13, further comprising:

another chip-scale package oriented at least partially over the active surface of the chip-scale package, the another chip-scale package including;

a semiconductor device; and

a plurality of contacts corresponding to the plurality of contacts of the chip-scale package, each chip-scale package contact of the plurality of contacts of the another chip-scale package including;

a bottom element extending over a portion of a back side of the semiconductor device; and

intermediate conductive elements operably coupled between the upper element of at least some chip-scale package contacts of the chip-scale package and at least the bottom element of a corresponding chip-scale package contact of the another chip-scale package.

15. The semiconductor device assembly of claim 14, wherein the electronic device component comprises a redistribution carrier having a chip-bearing surface.

16. The semiconductor device assembly of claim 15, wherein the redistribution carrier includes a back side opposite the chip-bearing surface.

17. The semiconductor device assembly of claim 16, further comprising:

a carrier substrate; and

intermediate conductive elements electrically coupling terminals of the carrier substrate to corresponding terminals of the redistribution carrier.

18. The semiconductor device assembly of claim 17, wherein the redistribution carrier is superimposed over at least a portion of the carrier substrate, terminals of the redistribution carrier are substantially aligned with corresponding terminals of the carrier substrate, and the intermediate conductive elements are disposed between substantially aligned pairs of corresponding terminals of the redistribution element and the carrier substrate.

19. The semiconductor device assembly of claim 13, wherein the chip-scale package further includes:

a redistribution layer over an active surface of the semiconductor device extending between bond pads of the semiconductor device and upper elements of contacts of the plurality of contacts;

a peripheral dielectric coating covering at least a portion of an outer lateral periphery of the semiconductor device, the peripheral dielectric coating including an edge adjacent to a junction between a lateral periphery and a back side of the semiconductor device;

a back side dielectric coating on at least a portion of the back side of the semiconductor device and including a peripheral edge abutting and forming a discernable boundary with a major surface of the peripheral dielectric coating;

the peripheral element of each chip-scale package contact being carried by the peripheral dielectric coating, spaced apart from the back side dielectric coating by the peripheral dielectric coating, and including an end adjacent to the edge of the peripheral dielectric coating; and

the bottom element of each chip-scale package contact carried partially by the back side dielectric coating, the edge of the peripheral dielectric coating and the end of the peripheral element abutting and forming a discernable boundary with a peripheral edge of the bottom element.

20. The semiconductor device assembly of claim 13, wherein the chip-scale package further includes:

a redistribution layer over an active surface of the semiconductor device extending from bond pads of the semiconductor device to upper elements of contacts of the plurality of contacts of the semiconductor device; and

a peripheral dielectric coating covering at least a portion of an outer lateral periphery of the semiconductor device between the active surface and back side of the semiconductor device under the peripheral elements of the plurality of contacts of the semiconductor device;

a back side dielectric coating on at least a portion of the back side of the semiconductor device and including a peripheral edge abutting and forming a discernable boundary with the peripheral dielectric coating; and

the bottom element of each chip-scale package contact extending over a portion of the back side dielectric coating.