High frequency receiver preamplifier with CMOS rail-to-rail capability

• US 8,063,702 B2
• Filed: 08/05/2010
• Issued: 11/22/2011
• Est. Priority Date: 12/02/2004
• Status: Expired due to Fees

• Current Assignee: Karmic Design-USA, LLC
• Original Assignee: Intelligent Design Limited
• Inventors: Lim, Hong Sair
• Primary Examiner(s): SHINGLETON, MICHAEL B
• Application Number:
  US12/806,095
• Publication Number:
  US 20100301939A1
• Time in Patent Office: 474 Days
• Field of Search: 330/253, 330/255, 330/311
• US Class Current: 330/253
• CPC Class Codes: H03F 2200/451 the amplifier being a radio frequency amplifier
• CPC Class Codes: H03F 2203/45054 the cascode stage of the cascode dif amp being a current mirror
• CPC Class Codes: H03F 2203/45496 the CSC comprising one or more extra resistors
• CPC Class Codes: H03F 2203/45641 the LC being controlled, e.g. by a signal derived from a non specified place in the dif amp circuit
• CPC Class Codes: H03F 3/189 High-frequency amplifiers, e.g. radio frequency amplifiers
• CPC Class Codes: H03F 3/45219 Folded cascode stages
• CPC Class Codes: H03F 3/45224 Complementary Pl types having parallel inputs and being supplied in parallel

Abstract

A folded cascode receiver amplifier with constant gain has inputs coupled to PMOS and NMOS differential transistors pairs with scaled geometries. The transconductance of both PMOS and NMOS transistors is the same whether the common mode input voltage is low or high. In a first version the transconductance of both PMOS and NMOS differential transistor pairs is reduced when the common mode input voltage is at mid-rail. Resistive means between current sources and the sources of the PMOS and NMOS transistor pairs force the current source transistors into the triode region of operation. A second version insures a constant voltage gain through control means which maintain a constant ratio of the transconductance of the output stage transistors versus the PMOS and NMOS differential transistor pairs when active.

Claims

1. A folded cascode receiver preamplifier with a CMOS rail-to-rail input, comprising:

a differential amplifier with PMOS and NMOS transistor pairs coupled to differential inputs and receiving a common mode input voltage, where the drains of said PMOS and NMOS transistor pairs are in communication with a summing output; and

an output stage coupled to said summing output of said differential amplifier, said output stage with a pair of load transistor stages each comprising at least one PMOS and NMOS output transistor in parallel, said load transistor stages controlled by differential control means responding to the level of said common mode input voltage, where said PMOS and NMOS output transistors are activated by said differential control means in correspondence with said PMOS and NMOS transistor pairs, respectively.

2. The folded cascode receiver preamplifier of claim 1, wherein the ratio of the transconductance of said differential amplifier versus said output stage is constant, and were thereby the gain of said differential amplifier coupled to said output stage is constant, regardless of the common mode input voltage.

3. The folded cascode receiver preamplifier of claim 1, wherein, when active, the ratio of the transconductance of each of said PMOS transistor pairs to the transconductance of each of said PMOS output transistors is the same.

4. The folded cascode receiver preamplifier of claim 1, wherein, when active, the ratio of the transconductance of each of said NMOS transistor pairs to the transconductance of each of said NMOS output transistors is the same.

5. The folded cascode receiver preamplifier of claim 1, wherein, when active, the ratio of the sum of the transconductance of said PMOS and NMOS transistor pairs to the sum of the transconductance of said PMOS and NMOS output transistors is the same.

6. A folded cascode receiver preamplifier with a CMOS rail-to-rail input, comprising:

an open-loop high frequency differential amplifier having differential inputs and differential current summing outputs, where at a low common mode input voltage only PMOS transistors are active and at a high common mode input voltage only NMOS transistors are active, and where at a middle input common mode voltage, between said low and said high input voltage both PMOS and NMOS transistors are active, said open-loop high frequency differential amplifier further comprising;

a level shifting stage comprising a transistor pair, said level shifting stage coupled to said differential inputs, said level shifting stage shifting the level of said differential inputs;

at least a PMOS differential input pair of transistors, where the gates of said PMOS differential input pair are coupled to the outputs of said level shifting stage, the drains of said PMOS differential input pair in communication with said differential current summing outputs, and where the sources of said PMOS differential input pair are in communication with each other;

at least an NMOS differential input pair of transistors for current summing, where the gates of said NMOS differential input pair are coupled to said differential inputs, where the sources of said NMOS differential input pair are in communication with each other, and where the drains of said NMOS differential input pair are coupled to said differential current summing outputs;

an output stage coupled to said differential current summing outputs to amplify signals of said differential current summing outputs, said output stage comprising diode-connected PMOS and NMOS transistors as the load for the positive and negative outputs of said output stage; and

voltage sensing stages for low and high common mode input voltage sensing, said voltage sensing stages coupled to said output stage, said voltage sensing stage comprising switching means to activate said diode-connected PMOS transistors when said common mode input voltage is low and to activate said diode-connected NMOS transistors when said common mode input voltage is high.

7. The folded cascode receiver preamplifier of claim 6, wherein the ratio of the transconductance of said open-loop high frequency differential amplifier versus said output stage is constant, and were thereby the gain of said differential amplifier coupled to said output stage is constant, regardless of the common mode input voltage.

8. The folded cascode receiver preamplifier of claim 6, wherein the PMOS and NMOS transistors of said PMOS and NMOS differential input pairs are scaled such that the transconductance of said PMOS and NMOS transistor is the same when active.

9. The folded cascode receiver preamplifier of claim 6, wherein the PMOS and NMOS transistors of said output stage are scaled such that the transconductance of said PMOS and NMOS transistor is the same when active.

10. The folded cascode receiver preamplifier of claim 6, wherein said differential current summing outputs sum the currents of said PMOS and NMOS differential input pairs.

11. The folded cascode receiver preamplifier of claim 6, wherein said low common mode input voltage ranges from said negative power supply up.

12. The folded cascode receiver preamplifier of claim 6, wherein said high common mode input voltage ranges from said positive power supply down.

13. A folded cascode receiver preamplifier with a CMOS rail-to-rail input, comprising:

an open-loop high frequency differential amplifier having differential inputs and differential current summing outputs, said open-loop differential amplifier receiving at said differential inputs a common mode input voltage, where at a low common mode input voltage only PMOS transistors are active and at a high common mode input voltage only NMOS transistors are active, and where at a middle input common mode voltage, between said low and said high input voltage both PMOS and NMOS transistors are active, said open-loop high frequency differential amplifier further comprising;

a level shifting stage comprising a transistor pair, said level shifting stage coupled to said differential inputs, said level shifting stage shifting the voltage level of said differential inputs;

at least a PMOS differential input pair of transistors, where the gates of said PMOS differential input pair are coupled to the outputs of said level shifting stage, the drains of said PMOS differential input pair in communication with said differential current summing outputs, and where the sources of said PMOS differential input pair are coupled via resistive means with each other to improve the linearity of said PMOS differential input pair;

at least an NMOS differential input pair of transistors for current summing, where the gates of said NMOS differential input pair are coupled to said differential inputs, where the sources of said NMOS differential input pair are coupled via resistive means with each other to improve the linearity of said NMOS differential input pair, and where the drains of said NMOS differential input pair are coupled to said differential current summing outputs;

a low voltage sensing stage comprising a differential input pair for performing low common mode input voltage sensing when said common mode input voltage is low, where the gates of said differential input pair of said first voltage sensing stage are coupled to the outputs of said level shifting stage;

a high voltage sensing stage comprising a differential input pair for performing high common mode input voltage sensing when said common mode input voltage is high, where the gates of said differential input pair of said first voltage sensing stage are coupled to said differential inputs; and

an output stage coupled to said differential current summing outputs and providing an amplified output, said output stage having a negative and a positive load transistor stage, each comprising diode-connected PMOS and NMOS transistors coupled in parallel as the load for the negative and positive outputs of said output stage, respectively, and where outputs of said low and high voltage sensing stage couple to gates of control transistors in series with said diode-connected PMOS and NMOS transistors, respectively, of said negative and positive load transistor stage, whereby said voltage sensing stages activate said diode-connected PMOS and NMOS transistors of said negative and positive load transistor stage in correspondence with said PMOS and NMOS differential input pair of transistors.

14. The folded cascode receiver preamplifier of claim 13, wherein the ratio of the transconductance of said open-loop high frequency differential amplifier versus said output stage is constant, and were thereby the gain of said differential amplifier coupled to said output stage is constant, regardless of said common mode input voltage.

15. The folded cascode receiver preamplifier of claim 13, wherein said differential current summing outputs are summing the currents of said PMOS and NMOS differential input pairs.

16. The folded cascode receiver preamplifier of claim 13, wherein, when active, the ratio of the transconductance of each of said PMOS transistor pairs to the transconductance of each of said diode-connected PMOS transistors is the same.

17. The folded cascode receiver preamplifier of claim 13, wherein, when active, the ratio of the transconductance of each of said NMOS transistor pairs to the transconductance of each of said diode-connected NMOS transistors is the same.

18. The folded cascode receiver preamplifier of claim 13, wherein, when active, the ratio of the sum of the transconductance of said PMOS and NMOS transistor pairs to the sum of the transconductance of said diode-connected PMOS and NMOS transistors is the same.

19. The folded cascode receiver preamplifier of claim 13, wherein said summing currents of said PMOS differential input pair are generated by coupling the drains of said PMOS differential input pair to gates of a transistors pair and the drains of said transistor pair to said differential current summing outputs, respectively.

20. The folded cascode receiver preamplifier of claim 13, wherein said low common mode input voltage ranges from said negative power supply up.

21. The folded cascode receiver preamplifier of claim 13, wherein said high common mode input voltage ranges from said positive power supply down.

22. The folded cascode receiver preamplifier of claim 13, wherein PMOS and NMOS transistors of said output stage are scaled such that the transconductance of said PMOS and NMOS transistor is the same when active.

23. The folded cascode receiver preamplifier of claim 13, wherein said PMOS differential input pair of transistors operate in the saturation region when said common mode input voltage is low.

24. The folded cascode receiver preamplifier of claim 13, wherein the inputs to said low voltage sensing stage are coupled to the outputs of said level shifting stage.

25. The folded cascode receiver preamplifier of claim 13, wherein the inputs to said high voltage sensing stage are coupled to said differential inputs.

26. A method of maintaining a constant voltage gain over a large common mode input voltage range for a high frequency receiver preamplifier with rail-to-rail capability, comprising the steps of:

a) providing an open-loop differential preamplifier with PMOS and NMOS input transistor pairs and differential current summing outputs;

b) coupling an output stage to said differential current summing outputs;

c) activating PMOS and NMOS output transistors of said output stage via control means in correspondence with said PMOS and NMOS input transistor pairs; and

d) keeping constant the ratio of the transconductance of said PMOS and NMOS output transistors divided by the transconductance of said PMOS and NMOS input transistor pairs.

27. The method of claim 26, wherein resistive means coupled between the sources of said PMOS and NMOS input transistors pairs, respectively, improve the linearity of the transconductance of said PMOS and NMOS input transistors pairs.