Solid-state imaging apparatus and operation for controlling the output of image signals to allow time for an external circuit to process the image signals

• US 8,063,962 B2
• Filed: 03/09/2009
• Issued: 11/22/2011
• Est. Priority Date: 03/07/2008
• Status: Active Grant

• Current Assignee: Olympus Corporation
• Original Assignee: Olympus Corporation
• Inventors: Hagihara, Yoshio
• Primary Examiner(s): HERNANDEZ, NELSON D
• Application Number:
  US12/400,075
• Publication Number:
  US 20090231476A1
• Time in Patent Office: 988 Days
• Field of Search: 348300-308
• US Class Current: 348/304
• CPC Class Codes: H04N 23/51 Housings
• CPC Class Codes: H04N 23/555 for picking-up images in sites, inaccessible due to their dimensions or hazardous conditions, e.g. endoscopes or borescopes
• CPC Class Codes: H04N 25/702 SSIS architectures characterised by non-identical, non-equidistant or non-planar pixel layout
• CPC Class Codes: H04N 25/75 Circuitry for providing, modifying or processing image signals from the pixel array

Abstract

A solid-state imaging apparatus including: an imaging section having pixels arranged into a matrix; a conversion section for digitizing pixel signals; a block memory section formed of a first line memory corresponding to at least N lines (N being an integral number of 2 or more) for retaining the pixel signals; and a drive control section for controlling so as to read out and cause to be retained at the block memory section pixel signals corresponding to M lines (M being an integral number between 2 and N inclusive) in a period shorter than period necessary for an external circuit to process pixel signals corresponding to 1 line, and then controlling so as to bring into halt condition at least one of imaging section and conversion section in a remaining period in the period necessary for external circuit to process pixel signals corresponding to M lines.

Claims

1. A solid-state imaging apparatus comprising:

an imaging section having pixels arranged into a matrix each pixel for outputting a pixel signal corresponding to an amount of an incident electromagnetic wave;

a conversion section for digitizing pixel signals outputted from said imaging section;

a block memory section formed of a first line memory corresponding to at least N lines (N being an integral number of 2 or more) for retaining said digitized pixel signals; and

a drive control section for controlling so as to read out and cause to be retained at said block memory section pixel signals corresponding to M lines (M being an integral number between 2 and N inclusive) of said imaging section in a period shorter than a period necessary for an external circuit receiving said pixel signals read out from said block memory section to process pixel signals corresponding to 1 line so that the number of transitions from a halt condition to an operational condition is fewer than when said operational condition and said halt condition are sequentially executed, and then controlling so as to bring into the halt condition at least one of said imaging section and said conversion section in a remaining period in a period necessary for the external circuit to process pixel signals corresponding to the M lines,

wherein said drive control section, after consecutively reading out said pixel signals corresponding to N lines and causing them to be retained at said block memory section, effects control so as to bring at least one of said imaging section and said conversion section into the halt condition in a period remaining until a period necessary for the external circuit to process pixel signals corresponding to N lines.

2. The solid-state imaging apparatus according to claim 1, wherein said block memory section uses a part of a second line memory for retaining pixel signals for use in a detection/correction of defect.

3. A capsule type endoscope comprising:

the solid-state imaging apparatus according to claim 1; and

a circuit for processing said pixel signals from said solid-state imaging apparatus.

4. A capsule type endoscope comprising:

the solid-state imaging apparatus according to claim 2; and

a circuit for processing said pixel signals from said solid-state imaging apparatus.