Architecture of a nvDRAM array and its sense regime
First Claim
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1. A memory system comprising:
- a plurality of nvDRAM cells;
a plurality of sense amplifiers; and
the nvDRAM cells comprising a single data interface, the single data interface coupling the nvDRAM cells to the sense amplifiers, the sense amplifiers configured to operate with current sensing during RECALL operations, and with differential voltage sensing otherwise.
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Abstract
A process of operating a memory array includes performing all volatile and nonvolatile operations on an nvDRAM cell array via a single data interface and using only DRAM-level signals on the data interface.
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Citations
14 Claims
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1. A memory system comprising:
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a plurality of nvDRAM cells; a plurality of sense amplifiers; and the nvDRAM cells comprising a single data interface, the single data interface coupling the nvDRAM cells to the sense amplifiers, the sense amplifiers configured to operate with current sensing during RECALL operations, and with differential voltage sensing otherwise. - View Dependent Claims (2, 3, 9, 10)
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4. A device comprising:
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at least one processor, and a memory system comprising a plurality of nvDRAM cells and a plurality of sense amplifiers, the nvDRAM cells comprising a single data interface, the single data interface coupling the nvDRAM cells to the sense amplifiers, the sense amplifiers configured to operate with current sensing during RECALL operations, and with differential voltage sensing otherwise. - View Dependent Claims (5, 6, 11, 12)
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7. A process of operating a memory array comprising:
performing all volatile and nonvolatile operations on an nvDRAM cell array via a single data interface and operating sense amplifiers with current sensing during RECALL operations, and with differential voltage sensing otherwise. - View Dependent Claims (8, 13, 14)
Specification