Architecture of a nvDRAM array and its sense regime

• US 8,064,255 B2
• Filed: 12/31/2007
• Issued: 11/22/2011
• Est. Priority Date: 12/31/2007
• Status: Active Grant

• Current Assignee: Monterey Research, LLC (Vector Capital Corporation)
• Original Assignee: Cypress Semiconductor Corporation (Infineon Technologies AG)
• Inventors: Scade, Andreas, Guenther, Stefan
• Primary Examiner(s): MAI, SON LUU
• Application Number:
  US12/006,226
• Publication Number:
  US 20090168519A1
• Time in Patent Office: 1,422 Days
• Field of Search: 365/185.08
• US Class Current: 365/185.08
• CPC Class Codes: G11C 11/405 with three charge-transfer gates, e.g. MOS transistors, per cell
• CPC Class Codes: G11C 11/4063 Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
• CPC Class Codes: G11C 11/4097 Bit-line organisation, e.g. bit-line layout, folded bit lines
• CPC Class Codes: G11C 14/00 Digital stores characterised by arrangements of cells having volatile and non-volatile storage properties for back-up when the power is down
• CPC Class Codes: G11C 14/0018 whereby the nonvolatile element is an EEPROM element, e.g. a floating gate or metal-nitride-oxide-silicon [MNOS] transistor

Abstract

A process of operating a memory array includes performing all volatile and nonvolatile operations on an nvDRAM cell array via a single data interface and using only DRAM-level signals on the data interface.

Claims

1. A memory system comprising:

a plurality of nvDRAM cells;

a plurality of sense amplifiers; and

the nvDRAM cells comprising a single data interface, the single data interface coupling the nvDRAM cells to the sense amplifiers, the sense amplifiers configured to operate with current sensing during RECALL operations, and with differential voltage sensing otherwise.

2. The memory system of claim 1, wherein the plurality of nvDRAM cells further comprising:

each nvDRAM cell comprising a pair of charge cells, one charge cell coupled to a true bit line and not to a complement bit line, the other coupled to the complement bit line and not to the true bit line.

3. The memory system of claim 1, further comprising:

the nvDRAM cells comprising a single control interface, the single control interface comprising a single higher than DRAM level control signal line.

9. The memory system of claim 1, further comprising:

an additional current source to the nvDRAM cells that is switched on during RECALL and switched off otherwise.

10. The memory system of claim 1, further comprising:

an additional current source to the nvDRAM cells that is switched on during RECALL and one or more of STORE and ERASE, and switched off otherwise.

4. A device comprising:

at least one processor, and

a memory system comprising a plurality of nvDRAM cells and a plurality of sense amplifiers, the nvDRAM cells comprising a single data interface, the single data interface coupling the nvDRAM cells to the sense amplifiers, the sense amplifiers configured to operate with current sensing during RECALL operations, and with differential voltage sensing otherwise.

5. The device of claim 4, wherein the plurality of nvDRAM cells further comprises:

each nvDRAM cell comprising a pair of charge cells, one charge cell coupled to a true bit line and not to a complement bit line, the other coupled to the complement bit line and not to the true bit line.

6. The device of claim 4, further comprising:

the nvDRAM cells comprising a single control interface, the single control interface comprising a single higher than DRAM level control signal line.

11. The device of claim 4, further comprising:

an additional current source to the nvDRAM cells that is switched on during RECALL and switched off otherwise.

12. The device of claim 4, further comprising:

an additional current source to the nvDRAM cells that is switched on during RECALL and one or more of STORE and ERASE, and switched off otherwise.

7. A process of operating a memory array comprising:

performing all volatile and nonvolatile operations on an nvDRAM cell array via a single data interface and operating sense amplifiers with current sensing during RECALL operations, and with differential voltage sensing otherwise.

8. The process of operating a memory array of claim 7, further comprising:

using only a single control line for all control signals to the nvDRAM that exceed DRAM levels.

13. The process of claim 7, further comprising:

applying an additional current source to cells of the nvDRAM during RECALL, and switching off the current source otherwise.

14. The process of claim 7, further comprising:

applying an additional current source to cells of the nvDRAM during RECALL and one or more of STORE and ERASE, and switching off the current source otherwise.