Using on-chip and off-chip look-up tables indexed by instruction address to control instruction execution in a processor

• US 8,065,504 B2
• Filed: 12/02/2004
• Issued: 11/22/2011
• Est. Priority Date: 01/28/1999
• Status: Expired due to Fees

• Current Assignee: Advanced Silicon Technologies LLC
• Original Assignee: ATI International SRL (Advanced Micro Devices, Inc.)
• Inventors: Yates, Jr., John S., Reese, David L., Hohensee, Paul H., Van Dyke, Korbin S., Thusoo, Shalesh, Ramesh, Tiruvur R.
• Primary Examiner(s): ELLIS, RICHARD L
• Application Number:
  US11/004,729
• Publication Number:
  US 20050086451A1
• Time in Patent Office: 2,546 Days
• Field of Search: 712/209, 712/227, 703/26, 703/27, 717/134, 717/138
• US Class Current: 712/209
• CPC Class Codes: G06F 9/45533 Hypervisors; Virtual machine monitors

Abstract

A microprocessor chip has instruction pipeline circuitry, and instruction classification circuitry that classifies instructions as they are executed into a small number of classes and records a classification code value. An on-chip table has entries corresponding to a range of addresses of a memory and designed to hold a statistical assessment of a value of consulting an off-chip table in a memory of the computer. Lookup circuitry is designed to fetch an entry from the on-chip table as part of the basic instruction processing cycle of the microprocessor. A mask has a value set at least in part by a timer. The instruction pipeline circuitry is controlled based on the value of the on-chip table entry corresponding to the address of instructions processed, the current value of the mask, the recorded classification code, and the off-chip table.

Claims

1. A microprocessor chip, comprising:

instruction pipeline circuitry;

instruction classification circuitry responsive to execution of instructions executed by the instruction pipeline circuitry to classify the executed instructions into a small number of classes and record a classification code value;

an on-chip table, each entry of the on-chip table corresponding to a range of addresses of a memory of the computer and designed to hold a statistical assessment of a value of consulting an off-chip table in a memory of the computer;

lookup circuitry designed to fetch an entry from a on-chip table as part of the basic instruction processing cycle of the microprocessor;

a mask whose value is set at least in part by a timer;

pipeline control circuitry designed to consult the on-chip table and to control processing of instructions by the instruction pipeline circuitry as part of the basic instruction processing cycle of the microprocessor, depending, at least in part, on the value of the on-chip table entry corresponding to the address of an instruction processed by the instruction pipeline circuitry, the current value of the mask, and the recorded classification code; and

control circuitry and/or software designed to cooperate with the instruction pipeline circuitry and pipeline control circuitry to control operation of the instruction pipeline circuitry based on consultation of the off-chip table after a favorable value is obtained from the on-chip table.

2. A microprocessor chip, comprising:

instruction pipeline circuitry;

lookup circuitry designed to fetch an entry from a lookup structure as part of the basic instruction processing cycle of the microprocessor, each entry of the lookup structure being associated with a corresponding address range accessed by the microprocessor;

a mask whose value is set at least in part by a timer;

pipeline control circuitry designed to control processing of instructions by the instruction pipeline circuitry as part of the basic instruction processing cycle of the microprocessor, depending, at least in part, on the value of the entry corresponding to the address range in which lies an instruction processed by the instruction pipeline circuitry, and the current value of the mask.

3. The microprocessor chip of claim 2:

further comprising a binary translator programmed to translate at least a selected portion of a computer program from a first binary representation to a second binary representation;

wherein the pipeline control circuitry is further designed to initiate a determination of whether to transfer control from an execution of the first binary representation of the program to the second, and effective to initiate the determination with neither a query nor a transfer of control to the second binary representation being coded into the first binary representation.

4. The microprocessor chip of claim 2:

wherein the pipeline control circuitry is further designed to recognize, as part of executing an instruction, that an alternate coding of the instruction exists, the recognizing being initiated without executing a transfer of control to the alternate coding or a query instruction;

and further comprising circuitry and/or software designed to abort the execution of the instruction when an alternate coding exists, and to transfer control to the alternate coding.

5. The microprocessor chip of claim 2:

further comprising instruction classification circuitry responsive to execution of instructions executed by the instruction pipeline circuitry to classify the executed instructions into a small number of classes and record a classification code value;

wherein the pipeline control circuitry is further designed to control processing of instructions by the instruction pipeline circuitry depending, at least in part, on the recorded classification code.

6. The microprocessor chip of claim 5:

wherein the lookup structure comprises an on-chip table, the on-chip table designed to hold an approximately-correct evaluation of a portion of the microprocessor machine state for control of the circuitry;

wherein the pipeline control circuitry is further designed to control processing of instructions by the instruction pipeline circuitry based on consultation of the on-chip table.

7. The microprocessor chip of claim 2, wherein the lookup circuitry and lookup structure are part of a content-addressable memory interconnected with instruction fetch circuitry of the microprocessor chip to monitor addresses of instructions fetched for execution by the instruction pipeline circuitry.

8. The microprocessor chip of claim 7, wherein the content-addressable memory is a translation lookaside buffer.

9. The microprocessor chip of claim 2, wherein the lookup structure is loaded from a table of entries, each table entry describing a memory page of a memory system, the table organized as a side table to an address translation page table.

10. The microprocessor chip of claim 2, wherein the hookup structure is a bit vector.

11. The microprocessor chip of claim 2, wherein the control of instruction processing includes branch destination processing.

12. A microprocessor chip, comprising:

instruction pipeline circuitry;

instruction classification circuitry responsive to execution of instructions executed by the instruction pipeline circuitry to classify the executed instructions into a small number of classes and record a classification code value;

lookup circuitry designed to fetch an entry from a lookup structure as part of the basic instruction processing cycle of the microprocessor, each entry of the lookup structure being associated with a corresponding address range accessed by the microprocessor;

an on-chip table, each entry of the on-chip table corresponding to a range of addresses of the memory, the on-chip table designed to hold an approximately-correct evaluation of a portion of the microprocessor machine state for control of the circuitry, wherein error in the approximation of the on-chip table is induced by a slight time lag relative to the portion of the microprocessor'"'"'s machine state whose evaluation is stored therein; and

pipeline control circuitry designed to;

control processing of instructions by the instruction pipeline circuitry as part of the basic instruction processing cycle of the microprocessor, depending, at least in part, on the value of the entry corresponding to the address range in which the instruction address lies and the recorded classification code; and

control processing of instructions by the instruction pipeline circuitry based on consultation of the on-chip table as part of the basic instruction processing cycle of the microprocessor.

13. A microprocessor chip, comprising:

instruction pipeline circuitry;

instruction classification circuitry responsive to execution of instructions executed by the instruction pipeline circuitry to classify the executed instructions into a small number of classes and record a classification code value;

lookup circuitry designed to fetch an entry from a lookup structure as part of the basic instruction processing cycle of the microprocessor, each entry of the lookup structure being associated with a corresponding address range accessed by the microprocessor, wherein the address ranges correspond to entries in an interrupt vector table; and

pipeline control circuitry designed to control processing of instructions by the instruction pipeline circuitry as part of the basic instruction processing cycle of the microprocessor, depending, at least in part, on the value of the entry corresponding to the address range in which the instruction address lies, and the recorded classification code.

14. A microprocessor chip, comprising:

instruction pipeline circuitry;

instruction classification circuitry responsive to execution of instructions executed by the instruction pipeline circuitry to classify the executed instructions into a small number of classes and record a classification code value;

lookup circuitry designed to fetch an entry from a lookup structure as part of the basic instruction processing cycle of the microprocessor, each entry of the lookup structure being associated with a corresponding address range accessed by the microprocessor; and

pipeline control circuitry designed to control processing of instructions by the instruction pipeline circuitry as part of the basic instruction processing cycle of the microprocessor, depending, at least in part, on the value of the entry corresponding to the address range in which the instruction address lies and the recorded classification code, wherein bits of the entry corresponding to the address range in which the instruction address lies are AND'"'"'ed with corresponding bits of a mask associated with the instruction pipeline circuitry.

15. A microprocessor chip, comprising:

instruction pipeline circuitry;

an on-chip table, each entry of the on-chip table corresponding to a respective class of event occurring in the microprocessor and designed to hold an approximate and inexact evaluation of a portion of the microprocessor machine state for control of the circuitry, wherein error in the approximation of the on-chip table is induced by a slight time lag relative to the portion of the microprocessor'"'"'s machine state whose evaluation is stored therein; and

pipeline control circuitry designed to cooperate with the instruction pipeline circuitry to control processing of instructions by the instruction pipeline circuitry as part of the basic instruction processing cycle of the microprocessor, based on consultation of the on-chip table.

16. A microprocessor chip, comprising:

instruction pipeline circuitry;

an on-chip table, each entry of the on-chip table corresponding to a respective class of event occurring in the microprocessor and designed to hold an approximate and inexact evaluation of a portion of the microprocessor machine state for control of the circuitry;

lookup circuitry designed to fetch an entry from a lookup structure, each entry of the lookup structure being associated with a corresponding address range accessed by the microprocessor;

a mask whose value is set at least in part by a timer; and

pipeline control circuitry designed to;

cooperate with the instruction pipeline circuitry to control processing of instructions by the instruction pipeline circuitry as part of the basic instruction processing cycle of the microprocessor, based on consultation of the on-chip table; and

control processing of instructions by the instruction pipeline circuitry depending, at least in part, on the value of the entry corresponding to the address range in which lies an instruction processed by the instruction pipeline circuitry, and the current value of the mask.

17. The microprocessor chip of claim 16, wherein the lookup circuitry and lookup structure are part of a content-addressable memory interconnected with instruction fetch circuitry of the microprocessor chip to monitor addresses of instructions fetched for execution by the instruction pipeline circuitry.

18. The microprocessor chip of claim 16, wherein the on-chip table is loaded from a table of entries, each entry of the table describing a memory page of a memory system, the table organized as a side table to an address translation page table.

19. A microprocessor chip, comprising:

instruction pipeline circuitry;

an on-chip table, each entry of the on-chip table corresponding to a respective class of event occurring in the microprocessor and designed to hold an approximate and inexact evaluation of a portion of the microprocessor machine state for control of the circuitry, wherein the classes of events are classes of interrupt; and

pipeline control circuitry designed to cooperate with the instruction pipeline circuitry to control processing of instructions by the instruction pipeline circuitry as part of the basic instruction processing cycle of the microprocessor, based on consultation of the on-chip table.

20. A microprocessor chip, comprising:

instruction pipeline circuitry;

an on-chip table, each entry of the on-chip table corresponding to a respective class of event occurring in the microprocessor, and designed to hold an approximate and inexact evaluation of a portion of the microprocessor machine state for control of the circuitry, wherein bits of an entry of the on-chip table are AND'"'"'ed with corresponding bits of a mask associated with the instruction pipeline circuitry; and

pipeline control circuitry designed to cooperate with the instruction pipeline circuitry to control processing of instructions by the instruction pipeline circuitry as part of the basic instruction processing cycle of the microprocessor, based on consultation of the on-chip table.

21. A microprocessor chip, comprising:

instruction pipeline circuitry;

an on-chip table, each entry of the on-chip table corresponding to a class of event occurring the in the microprocessor and designed to control consultation of an off-chip table in a memory accessed by the microprocessor when an event of the class occurs, wherein the classes of events are memory references to corresponding respective address ranges of the memory addressed by the microprocessor;

a mask whose value is set at least in part by a timer;

pipeline control circuitry designed to;

cooperate with the instruction pipeline circuitry to consult the on-chip table as part of the basic instruction processing cycle of the microprocessor, as the classified events occur in the microprocessor; and

control processing of instructions by the instruction pipeline circuitry depending, at least in part, on an address range in which lies an instruction processed by the instruction pipeline circuitry, the value of the on-chip table entry corresponding to the instruction address, and the current value of the mask; and

control circuitry and/or software designed to cooperate with the instruction pipeline circuitry and pipeline control circuitry to affect a manipulation of data or transfer of control defined for the event in the instruction pipeline circuitry based on consultation of the off-chip table after a favorable value is obtained from the on-chip table.

22. The microprocessor chip of claim 21:

further comprising instruction classification circuitry responsive to execution of instructions executed by the instruction pipeline circuitry to classify the executed instructions into a small number of classes and record a classification code value;

wherein the pipeline control circuitry is further designed to control processing of instructions by the instruction pipeline circuitry depending, at least in part, on the recorded classification code.

23. A method, comprising the steps of:

executing a computer program in instruction pipeline circuitry of a microprocessor, the microprocessor having lookup circuitry designed to fetch an entry from a lookup structure as part of the basic instruction processing cycle of the microprocessor, entries of the lookup structure being indexed by a corresponding address ranges of addresses generated by the microprocessor;

as part of the basic instruction processing cycle of the microprocessor, controlling processing of instructions by the instruction pipeline circuitry based at least in part on the value of the entry corresponding to the address range in which lies an instruction processed by the instruction pipeline circuitry, and the current value of a mask, the mask having a value set at least in part by a timer.

24. The method of claim 23, further comprising the step of:

indexing into a lookup structure having entries each corresponding to a respective class of event occurring in the microprocessor, and designed to hold an approximate and inexact evaluation of a portion of the microprocessor machine state for control of the circuitry.

25. The method of claim 23, further comprising the step of:

as part of the basic instruction processing cycle of the microprocessor, consulting an on-chip table within the microprocessor, each entry of the on-chip table corresponding to a class of event occurring the in the instruction pipeline circuitry and designed to control consultation of an off-chip table in a memory accessed by the microprocessor when an event of the class occurs;

affecting a manipulation of data or transfer of control defined for the event in the instruction pipeline circuitry based on consultation of the off-chip table after a favorable value is obtained from the on-chip table.

26. A method, comprising the steps of:

storing information in a slow representation in a computer memory;

generating a fast representation of portions of the information in the computer memory;

dividing the slow representation of the information into spatial blocks;

classifying elements of the information into logical classes;

forming a correspondence map from elements of the slow representation to corresponding elements in the fast representation, the correspondence map noting whether an element of the information has an extant fast representation, and if extant, providing an access key to the corresponding fast representation, the correspondence map being indexed by the spatial division and the logical classification of the information elements; and

as part of the basic instruction processing cycle of the computer, controlling processing of instructions by instruction pipeline circuitry of the computer, depending, at least in part, on the value of the fast representation corresponding to the address range in which the instruction being processed lies, and the current value of a mask whose value is set at least in part by a timer.

27. A microprocessor chip, comprising:

instruction pipeline circuitry;

instruction classification circuitry responsive to execution of instructions executed by the instruction pipeline circuitry to classify the executed instructions into a small number of classes and record a code value recording the classification;

lookup circuitry designed to fetch an entry from a lookup structure as part of the basic instruction processing cycle of the microprocessor, each entry of the lookup structure being associated with a corresponding address range accessed by the microprocessor; and

pipeline control circuitry designed to;

control processing of instructions by the instruction pipeline circuitry as part of the basic instruction processing cycle of the microprocessor, depending, at least in part, on the value of the entry corresponding to the address range in which the instruction address lies, and the recorded classification code; and

control processing of instructions by the instruction pipeline circuitry depending, at least in part, on the value of the entry corresponding to the address range in which lies an instruction processed by the instruction pipeline circuitry, and the current value of a mask whose value is set at least in part by a timer.