Data storage with an outer block code and a stream-based inner code

• US 8,065,583 B2
• Filed: 07/06/2007
• Issued: 11/22/2011
• Est. Priority Date: 07/06/2007
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Radke, William H.
• Primary Examiner(s): RIZK, SAMIR WADIE
• Application Number:
  US11/774,377
• Publication Number:
  US 20090013234A1
• Time in Patent Office: 1,600 Days
• Field of Search: 714/746, 714/752, 714/758
• US Class Current: 714/752
• CPC Class Codes: G06F 11/1068 in sector programmable memories, e.g. flash disk G06F11/1072 takes precedence
• CPC Class Codes: G11C 7/1006 Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor
• CPC Class Codes: H03M 13/2906 using block codes H03M13/2957 takes precedence
• CPC Class Codes: H03M 13/2933 using a block and a convolutional code H03M13/2957 takes precedence

Abstract

Apparatus and methods store stream-based error recovery data for a memory array, such as a NAND flash array. Conventionally, data is block coded per industry specification and stored in the memory array. Within the limits of the block code, this technique provides for correction of errors. By applying a stream-based inner code, that is, concatenating the outer block code with an outer code, the error correction can be further enhanced, enhancing the reliability of the device. This can also permit a relatively small-geometry device to be used in a legacy application.

Claims

1. An apparatus comprising:

one or more memory arrays for storage of data;

a stream-based coder configured to generate a page of forward error correction coded data of a page of original data intended for storage in the one or more memory arrays such that the coded page of data is larger than the page of original data and such that the original data is not recognizable in the coded data without decoding the coded data;

a page latch operatively coupled to the stream-based coder, wherein the page latch is at least large enough to hold the page of coded data for writing to the one or more memory arrays; and

a stream-based decoder configured to decode coded data retrieved from the one or more memory arrays to generate decoded data.

2. An apparatus comprising:

one or more memory arrays for storage of data;

a stream-based coder configured to generate a page of forward error correction coded data of a page of original data intended for storage in the one or more memory arrays such that the coded page of data is larger than the page of original data and such that the original data is not recognizable in the coded data without decoding the coded data;

a page latch operatively coupled to the stream-based coder, wherein the page latch is at least large enough to hold the page of coded data for writing to the one or more memory arrays;

a stream-based decoder configured to decode coded data retrieved from the one or more memory arrays to generate decoded data; and

a second page latch operatively coupled to the stream-based coder, wherein the second page latch is configured to store the page of original data for access by the stream-based coder for coding;

wherein the stream-based coder is configured to initiate a forward error correction process at least partially in response to an activation of a program page signal.

3. The apparatus of claim 2, further comprising:

a block code coder configured to generate block codes for forward error correction of data for storage, wherein the data and block codes comprise the original data coded by the stream-based coder; and

a block code decoder configured to further decode block codes of the decoded data from the stream-based decoder.

4. The apparatus of claim 2, wherein the stream-based decoder comprises a Viterbi decoder.

5. The apparatus of claim 2, wherein the stream-based coder comprises a convolution coder configured to XOR the original data to generate the coded data.

6. A method for storing data in a device having one or more memory arrays, the method comprising:

receiving block-coded data for storage in the one or more memory arrays, wherein the block-coded data comprises N bytes of page data and y bytes of block-type error correction data for the page data such that the block-coded data comprises N+y bytes of page data and block-type error correction data;

concatenating the N+y bytes of the block-coded data with a stream-based forward error correction code to generate a concatenated code that is a factor z times larger in size than the N+y bytes of original block-coded data such that the concatenated code has z(N+y) bytes; and

storing the concatenated code in the one or more memory arrays.

7. The method of claim 6, wherein concatenating comprises coding with a convolutional code.

8. The method of claim 6, wherein concatenating further comprises transparently coding such that a host device is unaware that the concatenating is taking place.

9. The method of claim 6, wherein the one or more memory array comprises one or more flash memory arrays.

10. The method of claim 6, further comprising:

temporarily storing a page of block-coded data;

determining an activation of a program page signal; and

initiating concatenating at least partially in response to the activation of the program page signal.