Method for packaging circuits

• US 8,065,792 B2
• Filed: 02/15/2010
• Issued: 11/29/2011
• Est. Priority Date: 05/06/2003
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Boon, Suan Jeung, Chua, Swee Kwang, Chia, Yong Poo, Koon, Eng Meow, Waf, Low Siu
• Primary Examiner(s): Nguyen; Donghai D.
• Application Number:
  US12/705,923
• Publication Number:
  US 20100146780A1
• Time in Patent Office: 652 Days
• Field of Search: 298/31, 298/32, 298/34, 298/40, 298/41, 298/46, 298/52, 298/53, 294/15, 174254-256, 174/260, 174/262, 257/684, 257/686, 257/698, 361/760, 361/783, 361/820
• US Class Current: 29/831
• CPC Class Codes: H01L 21/56 Encapsulations, e.g. encapsulation layers, coatings
• CPC Class Codes: H01L 21/561 Batch processing
• CPC Class Codes: H01L 21/568 Temporary substrate used as encapsulation process aid H01L21/4832 and H01L21/566 take precedence
• CPC Class Codes: H01L 21/6835 using temporarily an auxiliary support
• CPC Class Codes: H01L 22/00 Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
• CPC Class Codes: H01L 2221/68345 used as a support during the manufacture of self supporting substrates
• CPC Class Codes: H01L 2224/97 the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 2225/06524 Electrical connections formed on device or on substrate, e.g. a deposited or grown layer
• CPC Class Codes: H01L 2225/06541 Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV] manufacturing via connections per se H01L21/76898
• CPC Class Codes: H01L 2225/06548 Conductive via connections through the substrate, container, or encapsulation
• CPC Class Codes: H01L 2225/06551 Conductive connections on the side of the device
• CPC Class Codes: H01L 2225/06558 the devices having passive surfaces facing each other, i.e. in a back-to-back arrangement
• CPC Class Codes: H01L 2225/06575 Auxiliary carrier between devices, the carrier having no electrical connection structure
• CPC Class Codes: H01L 23/3114 the device being a chip scale package, e.g. CSP
• CPC Class Codes: H01L 24/05 of an individual bonding area
• CPC Class Codes: H01L 24/97 the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 25/0657 Stacked arrangements of devices
• CPC Class Codes: H01L 25/50 Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/12042 LASER
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: Y10T 29/49128 : Assembling formed circuit to base
• CPC Class Codes: Y10T 29/4913 : Assembling to base an electrical component, e.g., capacitor, etc.
• CPC Class Codes: Y10T 29/49144 : by metal fusion
• CPC Class Codes: Y10T 29/49146 : with encapsulating, e.g., potting, etc.
• CPC Class Codes: Y10T 29/49155 : Manufacturing circuit on or in base
• CPC Class Codes: Y10T 29/49165 : by forming conductive walled aperture in base
• CPC Class Codes: Y10T 29/49167 : with deforming of conductive path
• CPC Class Codes: Y10T 29/49169 : Assembling electrical component directly to terminal or elongated conductor
• CPC Class Codes: Y10T 29/49794 : Dividing on common outline

Abstract

A method for packaging integrated circuit chips (die) is described that includes providing a base substrate with package level contacts, coating a base substrate with adhesive, placing dies on the adhesive, electrically connecting the die to the package level contacts, and removing the backside of the base substrate to expose the backside of the package level contacts. Accordingly, an essentially true chip scale package is formed. Multi-chip modules are formed by filling gaps between the chips with an encapsulant. In an embodiment, chips are interconnected by electrical connections between package level contacts in the base substrate. In an embodiment, substrates each having chips are adhered back-to-back with through vias formed in aligned saw streets to interconnect the back-to-back chip assembly.

Claims

1. A method, comprising:

curing adhesive to fix a first substrate to a second substrate, and to align first saw streets separating a plurality of first dice on the first substrate with second saw streets separating a plurality of second dice on the second substrate;

forming a plurality of through apertures in the aligned first and second saw streets;

forming electrical connections from the first dice on the first substrate to the second dice on the second substrate, wherein forming the electrical connections includes filling at least some of the plurality of through apertures with a conductive material; and

singulating aligned first and second dice from a remainder of the fixed first and second substrates, the electrical connections being substantially flush with smooth sides of the singulated aligned first and second dice.

2. The method of claim 1, wherein forming electrical connections from the first dice on the first substrate to the second dice on the second substrate includes routing a conductive trace from a first bond pad on an active device surface of the first substrate to a second bond pad on an active device surface of the second substrate through at least one of the through apertures.

3. The method of claim 1, comprising:

at least partially coating a base surface of the second substrate with the adhesive; and

contacting a base surface of the first substrate with the adhesive.

4. The method of claim 1, wherein forming the electrical connections includes forming metal traces.

5. The method of claim 4, wherein forming the metal traces includes forming a copper trace.

6. The method of claim 4, wherein forming the metal traces includes forming an aluminum trace.

7. The method of claim 1, wherein the singulating includes mechanically cutting the saw streets to form a side of the fixed first and second substrates.

8. The method of claim 7, wherein the singulating includes exposing at least one of the electrical connections along the side of the fixed first and second substrates.

9. The method of claim 7, wherein mechanically cutting the saw streets includes partially cutting some of the electrical connections in respective ones of the through apertures such that a portion of the cut electrical connections in the respective ones of the through apertures remain with the dice adjacent the respective ones of the through apertures.

10. A method, comprising:

curing adhesive to fix a first substrate to a second substrate, and to align first saw streets separating a plurality of first dice of a first active device surface of the first substrate with second saw streets separating a plurality of second dice of a second active device surface of the second substrate, the first and second active device surfaces forming exterior surfaces;

forming a plurality of through apertures in the aligned first and second saw streets;

forming electrical connections from the first dice on the first substrate to the second dice on the second substrate, wherein forming the electrical connections includes filling at least some of the plurality of through apertures with a conductive material; and

singulating aligned first and second dice from a remainder of the fixed first and second substrates, wherein the singulated aligned first and second dice include smooth sides including the electrical connections being substantially flush with the sides of the singulated aligned first and second dice.

11. The method of claim 10, wherein forming electrical connections from the first dice on the first substrate to the second dice on the second substrate includes routing a conductive trace from a first bond pad on the first active device surface to a second bond pad on the second active device surface through at least one of the through apertures.

12. The method of claim 10, comprising:

at least partially coating a base surface of the second substrate with the adhesive; and

contacting a base surface of the first substrate with the adhesive.

13. The method of claim 10, wherein forming the electrical connections includes forming metal traces comprising one of copper or aluminum.

14. The method of claim 10, wherein forming the electrical connections includes forming metal traces with a redistribution layer process.

15. The method of claim 14, wherein forming the metal traces with the redistribution layer process includes blanket depositing a metal distribution layer on the first and second substrates.

16. The method of claim 10, wherein the singulating includes lazing the saw streets to form the sides of the singulated aligned first and second dice.

17. The method of claim 16, wherein lazing the saw streets includes exposing at least one of the electrical connections along the side of the singulated aligned first and second dice.

18. The method of claim 16, wherein lazing the saw streets includes partially cutting some of the electrical connections in respective ones of the through apertures such that a portion of the cut electrical connections in the respective ones of the through apertures remain with the dice adjacent the respective ones of the through apertures.