Printed wiring board and its manufacturing method

• US 8,065,794 B2
• Filed: 09/26/2008
• Issued: 11/29/2011
• Est. Priority Date: 09/14/1998
• Status: Expired due to Term

• Current Assignee: Ibiden Co., Ltd.
• Original Assignee: Ibiden Co., Ltd.
• Inventors: Noda, Kouta, Oki, Takeo, Hirose, Naohiro, Nakai, Tohru, En, Honchin
• Primary Examiner(s): Norris; Jeremy
• Application Number:
  US12/239,306
• Publication Number:
  US 20090145652A1
• Time in Patent Office: 1,159 Days
• Field of Search: 29846-853
• US Class Current: 29/847
• CPC Class Codes: C23C 18/1607 by direct patterning
• CPC Class Codes: C23C 18/1653 Two or more layers with at least one layer obtained by electroless plating and one layer obtained by electroplating
• CPC Class Codes: C23C 18/22 Roughening, e.g. by etching
• CPC Class Codes: C23C 18/30 Activating or accelerating or sensitising with palladium or other noble metal
• CPC Class Codes: C23C 18/34 using reducing agents
• CPC Class Codes: C23C 18/405 Formaldehyde
• CPC Class Codes: C23C 28/00 Coating for obtaining at least two superposed coatings either by methods not provided for in a single one of groups C23C2/00 - C23C26/00 or by combinations of methods provided for in subclasses C23C and C25C or C25D
• CPC Class Codes: C23C 28/023 only coatings of metal elements only
• CPC Class Codes: C23C 28/42 characterized by the composition of the alternating layers
• CPC Class Codes: C25D 3/38 of copper
• CPC Class Codes: C25D 5/022 using masking means
• CPC Class Codes: C25D 5/18 Electroplating using modulated, pulsed or reversing current
• CPC Class Codes: C25D 5/34 Pretreatment of metallic surfaces to be electroplated
• CPC Class Codes: C25D 5/617 Crystalline layers
• CPC Class Codes: C25D 5/625 Discontinuous layers, e.g. microcracked layers
• CPC Class Codes: C25D 7/123 Semiconductors first coated with a seed layer or a conductive layer
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2924/15174 in different layers of the multilayer substrate
• CPC Class Codes: H01L 2924/15311 being a ball array, e.g. BGA
• CPC Class Codes: H05K 2201/0215 Metallic fillers
• CPC Class Codes: H05K 2201/0344 : Electroless sublayer, e.g. Ni, Co, Cd or Ag; Transferred electroless sublayer
• CPC Class Codes: H05K 2201/0347 : Overplating, e.g. for reinforcing conductors or bumps; Plating over filled vias
• CPC Class Codes: H05K 2201/09509 : Blind vias, i.e. vias having one side closed
• CPC Class Codes: H05K 2201/09536 : Buried plated through-holes, i.e. plated through-holes formed in a core before lamination
• CPC Class Codes: H05K 2201/09563 : Metal filled via
• CPC Class Codes: H05K 2201/0959 : Plated through-holes or plated blind vias filled with insulating material
• CPC Class Codes: H05K 2201/096 : Vertically aligned vias, holes or stacked vias
• CPC Class Codes: H05K 2203/0353 : Making conductive layer thin, e.g. by etching
• CPC Class Codes: H05K 2203/0723 : Electroplating, e.g. finish plating
• CPC Class Codes: H05K 2203/1476 : Same or similar kind of process performed in phases, e.g. coarse patterning followed by fine patterning
• CPC Class Codes: H05K 2203/1492 : Periodical treatments, e.g. pulse plating of through-holes
• CPC Class Codes: H05K 3/0038 : combined with laser drilling through a metal layer
• CPC Class Codes: H05K 3/108 : by semi-additive methods; masks therefor characterised by metallic etch mask H05K3/062; electroplating methods or apparatus H05K3/241
• CPC Class Codes: H05K 3/181 : by electroless plating adhesives therefor H05K3/387
• CPC Class Codes: H05K 3/241 : characterised by the electroplating method; means therefor, e.g. baths or apparatus
• CPC Class Codes: H05K 3/381 : by special treatment of the substrate
• CPC Class Codes: H05K 3/382 : by special treatment of the metal
• CPC Class Codes: H05K 3/384 : by plating
• CPC Class Codes: H05K 3/421 : Blind plated via connections H05K3/422, H05K3/423 and H05K3/425 take precedence
• CPC Class Codes: H05K 3/423 : characterised by electroplating method
• CPC Class Codes: H05K 3/427 : initial plating of through-holes in metal-clad substrates
• CPC Class Codes: H05K 3/4602 : characterized by a special circuit board as base or central core whereon additional circuit layers are built or additional circuit boards are laminated
• CPC Class Codes: H05K 3/4644 : by building the multilayer layer by layer, i.e. build-up multilayer circuits making via holes in the insulating layers H05K3/0011; special circuit boards as base or core whereon the multilayer is built H05K3/4602
• CPC Class Codes: H05K 3/4652 : Adding a circuit layer by laminating a metal foil or a preformed metal foil pattern H05K3/4647 takes precedence
• CPC Class Codes: H05K 3/4661 : Adding a circuit layer by direct wet plating, e.g. electroless plating; insulating materials adapted therefor other insulating materials H05K3/387
• CPC Class Codes: Y10T 29/49126 : Assembling bases
• CPC Class Codes: Y10T 29/49128 : Assembling formed circuit to base
• CPC Class Codes: Y10T 29/49155 : Manufacturing circuit on or in base
• CPC Class Codes: Y10T 29/49156 : with selective destruction of conductive paths
• CPC Class Codes: Y10T 29/49165 : by forming conductive walled aperture in base

Abstract

The present invention has for its object to provide a process for manufacturing multilayer printed circuit boards which is capable of simultaneous via hole filling and formation of conductor circuit and via holes of good crystallinity and uniform deposition can be constructed on a substrate and high-density wiring and highly reliable conductor connections can be realized without annealing. The present invention is related to a process for manufacturing multilayer printed circuit boards which comprises disposing an interlayer resin insulating layer on a substrate formed with a conductor circuit, creating openings for formation of via holes in said interlayer resin insulating layer, forming an electroless plated metal layer on said interlayer resin insulating layer, disposing a resist thereon, performing electroplating, stripping the resist off and etching the electroless plated metal layer to provide a conductor circuit and via holes, wherein the electroplating is performed intermittently using said electroless plated metal layer as cathode and a plating metal as anode at a constant voltage between said anode and said cathode.

Claims

1. A process for manufacturing a multilayer printed circuit board which comprises at least the following steps (1) to (4):

(1) a step for piercing through holes not larger than 200 μ

m in diameter in a core board by laser

(2) a step for plating said through holes therein to construct plated-through holes

(3) a step for constructing an interlayer resin insulating layer provided with openings communicating with said plated-through holes on the core board

(4) a step for plating the openings in said interlayer resin insulating layer to construct via holes in the manner of plugging the through holes in said plated-through holes.