Fabricating method for printed circuit board

• US 8,065,797 B2
• Filed: 09/05/2007
• Issued: 11/29/2011
• Est. Priority Date: 09/06/2006
• Status: Expired due to Fees

• Current Assignee: Samsung Electro-Mechanics Co., Ltd. (Samsung Group)
• Original Assignee: Samsung Electro-Mechanics Co., Ltd. (Samsung Group)
• Inventors: Watanabe, Ryoichi, Min, Byoung-Youl, Kim, Seung-Chul, Kang, Myung-San, Kim, Joon-Sung, Yoo, Je-Gwang
• Primary Examiner(s): ANGWIN, DAVID PATRICK
• Application Number:
  US11/896,774
• Publication Number:
  US 20080052905A1
• Time in Patent Office: 1,546 Days
• Field of Search: 298/52, 298/30, 298/31, 298/41, 298/46, 298/47, 174/250, 174/251, 174/255, 174/256, 174/257, 174/258
• US Class Current: 29/852
• CPC Class Codes: H05K 2201/0361 Etched tri-metal structure, i.e. metal layers or metal patterns on both sides of a different central metal layer which is later at least partly etched
• CPC Class Codes: H05K 2201/0376 Flush conductors, i.e. flush with the surface of the printed circuit
• CPC Class Codes: H05K 2201/09036 Recesses or grooves in insulating substrate recess in metallic substrate H05K2201/09745
• CPC Class Codes: H05K 2201/09563 Metal filled via plated through-hole filled with insulating material H05K2201/0959
• CPC Class Codes: H05K 2203/0278 Flat pressure, e.g. for connecting terminals with anisotropic conductive adhesive
• CPC Class Codes: H05K 2203/0384 Etch stop layer, i.e. a buried barrier layer for preventing etching of layers under the etch stop layer
• CPC Class Codes: H05K 2203/0582 Coating by resist, i.e. resist used as mask for application of insulating coating or of second resist
• CPC Class Codes: H05K 2203/1152 Replicating the surface structure of a sacrificial layer, e.g. for roughening
• CPC Class Codes: H05K 2203/1189 Pressing leads, bumps or a die through an insulating layer
• CPC Class Codes: H05K 2203/308 Sacrificial means, e.g. for temporarily filling a space for making a via or a cavity or for making rigid-flexible PCBs
• CPC Class Codes: H05K 3/0014 Shaping of the substrate, e.g. by moulding
• CPC Class Codes: H05K 3/0017 Etching of the substrate by chemical or physical means
• CPC Class Codes: H05K 3/045 by making a conductive layer having a relief pattern, followed by abrading of the raised portions
• CPC Class Codes: H05K 3/06 the conductive material being removed chemically or electrolytically, e.g. by photo-etch process semi-additive methods H05K3/108
• CPC Class Codes: H05K 3/107 by filling grooves in the support with conductive material H05K3/045, H05K3/101, H05K3/1258 and H05K3/465 take precedence
• CPC Class Codes: H05K 3/20 by affixing prefabricated conductor pattern H05K1/187, H05K3/046, H05K3/4658, H05K3/4682 takes precedence
• CPC Class Codes: H05K 3/205 using a pattern electroplated or electroformed on a metallic carrier
• CPC Class Codes: H05K 3/426 initial plating of through-holes in substrates without metal
• CPC Class Codes: H05K 3/4614 the electrical connections between the circuit boards being made during lamination
• CPC Class Codes: H05K 3/465 by applying an insulating layer having channels for the next circuit layer
• CPC Class Codes: H05K 3/4658 : characterized by laminating a prefabricated metal foil pattern, e.g. by transfer
• CPC Class Codes: Y10T 29/49126 : Assembling bases
• CPC Class Codes: Y10T 29/49155 : Manufacturing circuit on or in base
• CPC Class Codes: Y10T 29/49156 : with selective destruction of conductive paths
• CPC Class Codes: Y10T 29/49165 : by forming conductive walled aperture in base

Abstract

A method of fabricating a printed circuit board is disclosed. A method of fabricating a printed circuit board that includes: stacking an insulation layer on at least one surface of a core layer, on which an inner circuit is formed, and forming an outer circuit pattern; burying the outer circuit pattern in the insulation layer; removing the outer circuit pattern to form minute grooves and curing the insulation layer; and forming an outer circuit by filling metal in the minute grooves, makes it possible to readily form high-resolution fine-line circuits, as well as to reduce fabrication costs and increase productivity.

Claims

1. A method of fabricating a printed circuit board, the method comprising:

stacking an insulation layer on at least one surface of a core layer, the core layer having an inner circuit formed thereon;

forming a first outer circuit pattern on the insulation layer after the stacking;

pressing the first outer circuit pattern such that the first outer circuit pattern is buried in the insulation layer;

removing the first outer circuit pattern buried in the insulation layer such that minute grooves in correspondence with the first outer circuit pattern are formed in the insulation layer; and

forming a second outer circuit by filling metal in the minute grooves.

2. The method of claim 1, further comprising electrically connecting the second outer circuit and the inner circuit.

3. The method of claim 1, wherein the first outer circuit pattern is formed on the insulation layer by performing lithography with photoresist.

4. The method of claim 1, wherein the first outer circuit pattern is formed on a carrier by performing lithography with photoresist.

5. The method of claim 1, wherein the insulation layer is made of a thermosetting resin, and the insulation layer is in an uncured state during the burying.

6. The method of claim 1, wherein the insulation layer is made of a thermoplastic resin, and the first outer circuit pattern is transcribed into the insulation layer while the insulation layer is heated to a temperature above a transition temperature, during the burying.

7. The method of claim 1, wherein the first outer circuit pattern is removed by dissolving or swelling.

8. The method of claim 1, wherein forming the second outer circuit comprises, after filling the minute grooves using copper plating to form the second outer circuit, performing a planarization operation.

9. The method of claim 2, wherein the electrically connecting comprises, after removing the first outer circuit pattern, forming a via hole such that exposes a portion of the inner circuit and forming a plating layer on an inner perimeter of the via hole.

10. The method of claim 1, wherein at least one bump is formed on the first outer circuit pattern, the bump transcribed during the burying to be in contact with the inner circuit and then removed such that a hole is formed, and a plating layer is formed in an inner perimeter of the hole such that the inner circuit and the second outer circuit are electrically connected.