Method for fabricating at least one transistor

• US 8,067,269 B2
• Filed: 09/01/2006
• Issued: 11/29/2011
• Est. Priority Date: 10/19/2005
• Status: Expired due to Fees

• Current Assignee: Tinggi Technologies Pte., Ltd.
• Original Assignee: Tinggi Technologies Private Limited
• Inventors: Lin, Shi Ming, Kang, Xuejun, Yuan, Shu
• Primary Examiner(s): LE, DUNG ANH
• Application Number:
  US12/091,036
• Publication Number:
  US 20080224173A1
• Time in Patent Office: 1,915 Days
• Field of Search: 438122-125, 438705-720, 257192-195, 257712-706, 257 77- 79, 257 98-103
• US Class Current: 438/122
• CPC Class Codes: H01L 27/0605 integrated circuits made of compound material, e.g. AIIIBV
• CPC Class Codes: H01L 29/2003 Nitride compounds
• CPC Class Codes: H01L 29/66462 with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT

Abstract

A method for fabricating transistors such as high electron mobility transistors, each transistor comprising a plurality of epitaxial layers on a common substrate, method comprising: (a) forming a plurality of source contacts on a first surface of the plurality of epitaxial layers; (b) forming at least one drain contact on the first surface; (c) forming at least one gate contact on the first surface; (d) forming at least one insulating layer over and between the gate contacts, source contacts and the drain contacts; (e) forming a conductive layer over at least a part of the at least one insulating layer for connecting the source contacts; and (f) forming at least one heat sink layer over the conductive layer.

Claims

1. A method for fabricating transistors, each transistor comprising a plurality of epitaxial layers on a common substrate, the method comprising:

forming a plurality of source contacts on a first surface of the plurality of epitaxial layers;

forming at least one drain contact on the first surface;

forming at least one gate contact on the first surface;

forming at least one layer of insulating material over and between the at least one gate contact, the plurality of source contacts and the at least one drain contact for insulating the at least one gate contact, the plurality of source contacts and the at least one drain contact;

forming a conductive layer over and through at least a part of the at least one insulating layer, the conductive layer connecting the plurality of source contacts;

forming at least one seed layer on the conductive layer; and

forming at least one heat sink layer over the at least one seed layer; and

wherein the at least one seed layer is configured to buffer stresses of thermal expansion caused by the at least one heat sink layer.

2. The method as claimed in claim 1, wherein the transistors are high electron mobility transistors, the plurality of epitaxial layers comprising a layer of gallium nitride, a layer of aluminum gallium nitride, a layer of n+ aluminum gallium nitride and a final layer of gallium nitride, the first surface being on the final layer of gallium nitride, the at least one layer of insulating material being electrically insulating but heat conductive, the conductive layer connecting the plurality of source contacts through vias in the at least one layer of insulating material.

3. The method as claimed in claim 1, wherein the at least one heat sink layer is a relatively thick layer of conductive metal formed over the at least one seed layer, the relatively thick layer of conductive metal being for at least one selected from the group consisting of:

a structural support, a heat sink, a heat dissipater, and as a connector.

4. The method as claimed in claim 1, wherein the seed layer comprises a plurality of seed layers, wherein a first of the plurality of seed layers is applied to the conductive layer, the first of the plurality of seed layers being of a material that has a first co-efficient of thermal expansion, and a second seed layer is formed on the first of the plurality of seed layers, the second seed layer being of a material that has a second co-efficient of thermal expansion, the second co-efficient of thermal expansion being greater than the first co-efficient of thermal expansion, one of the first of the plurality of seed layers and the second seed layer being a diffusion barrier for providing a barrier to diffusion of a layer applied to it from diffusing into the epitaxial layers.

5. The method as claimed in claim 1, wherein a source connection is formed by creating then filling at least one via through the common substrate and the plurality of epitaxial layers to the conductive layer.

6. The method as claimed in claim 1, wherein a drain connection is formed by creating then filling at least one via through the common substrate and the plurality of epitaxial layers to the at least one drain contact, a gate connection is formed by creating then filling at least one via through the common substrate and the plurality of epitaxial layers to the at least one gate contact, and a source connection is formed by forming then filling at least one via through the plurality of epitaxial layers to the conductive layer.

7. The method as claimed in claim 1, further comprising removing the common substrate after the at least one heat sink layer is formed, and forming a further layer of electrically insulating and heat conductive material in place of the common substrate.

8. The method as claimed in claim 7, wherein a source connection is formed by forming then filling at least one via through the plurality of epitaxial layers to the conductive layer, a drain connection is formed by creating then filling at least one via through the plurality of epitaxial layers to the at least one drain contact, and a gate connection is formed by creating then filling at least one via through the plurality of epitaxial layers to the at least one gate contact.

9. The method as claimed in claim 1, wherein patterned plating is performed before the at least one heat sink layer is formed.