Thin film transistor with two gate electrodes

• US 8,067,775 B2
• Filed: 10/20/2009
• Issued: 11/29/2011
• Est. Priority Date: 10/24/2008
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Miyairi, Hidekazu, Yamazaki, Shunpei, Osada, Takeshi
• Primary Examiner(s): Dickey; Thomas L
• Assistant Examiner(s): YUSHIN, NIKOLAY K
• Application Number:
  US12/581,918
• Publication Number:
  US 20100102313A1
• Time in Patent Office: 770 Days
• Field of Search: 257/43, 257/72, 257/59, 257/E29.291, 257/E33.053, 257/9, 257/66, 257/E51.005
• US Class Current: 257/72
• CPC Class Codes: H01L 21/02565 Oxide semiconducting materials not being Group 12/16 materials, e.g. ternary compounds
• CPC Class Codes: H01L 21/47635 After-treatment of these layers
• CPC Class Codes: H01L 21/477 Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering H01L21/38 - H01L21/449 and H01L21/461 - H01L21/475 take precedence
• CPC Class Codes: H01L 27/1225 with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
• CPC Class Codes: H01L 27/1251 comprising TFTs having a different architecture, e.g. top- and bottom gate TFTs
• CPC Class Codes: H01L 27/1259 Multistep manufacturing methods
• CPC Class Codes: H01L 29/24 including, apart from doping materials or other impurities, only semiconductor materials not provided for in groups H01L29/16, H01L29/18, H01L29/20, H01L29/22 including organic materials H10K99/00
• CPC Class Codes: H01L 29/41733 for thin film transistors with insulated gate
• CPC Class Codes: H01L 29/42356 Disposition, e.g. buried gate electrode H01L29/42324 and H01L29/4234 take precedence
• CPC Class Codes: H01L 29/42384 for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor
• CPC Class Codes: H01L 29/45 Ohmic electrodes
• CPC Class Codes: H01L 29/66969 of devices having semiconductor bodies not comprising group 14 or group 13/15 materials comprising selenium or tellurium in uncombined form other than as impurities in semiconductor bodies of other materials, comprising cuprous oxide or cuprous iodide H01L21/02365
• CPC Class Codes: H01L 29/78621 with LDD structure or an extension or an offset region or characterised by the doping profile
• CPC Class Codes: H01L 29/78645 with multiple gate
• CPC Class Codes: H01L 29/78648 arranged on opposing sides of the channel
• CPC Class Codes: H01L 29/7869 having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate

Abstract

As a display device has a higher definition, the number of pixels, gate lines, and signal lines are increased. When the number of the gate lines and the signal lines are increased, a problem of higher manufacturing cost, because it is difficult to mount an IC chip including a driver circuit for driving of the gate and signal lines by bonding or the like. A pixel portion and a driver circuit for driving the pixel portion are provided over the same substrate, and at least part of the driver circuit includes a thin film transistor using an oxide semiconductor interposed between gate electrodes provided above and below the oxide semiconductor. Therefore, when the pixel portion and the driver portion are provided over the same substrate, manufacturing cost can be reduced.

Claims

1. A semiconductor device comprising:

a pixel portion; and

a driver circuit,

wherein the pixel portion includes at least a first thin film transistor including a first oxide semiconductor layer,

wherein the driver circuit includes at least a second thin film transistor including a second oxide semiconductor layer and a third thin film transistor including a third oxide semiconductor layer,

wherein the third thin film transistor includes a first gate electrode below the third oxide semiconductor layer and a second gate electrode above the third oxide semiconductor layer,

wherein the third oxide semiconductor layer includes a first region and a second region,

wherein the second region overlaps with a source or a drain electrode of the third thin film transistor,

wherein a thickness of the first region is smaller than a thickness of the second region, and

wherein the second thin film transistor is one of an enhancement type transistor and a depletion type transistor and the third thin film transistor is the other of the enhancement type transistor and the depletion type transistor.

2. The semiconductor device according to claim 1, wherein the first thin film transistor is electrically connected to a pixel electrode, and the pixel electrode is formed using the same material as the second gate electrode.

3. The semiconductor device according to claim 1, wherein the first thin film transistor is electrically connected to a pixel electrode, and the pixel electrode is formed using a different material from the second gate electrode.

4. The semiconductor device according to claim 1, wherein the third oxide semiconductor layer overlaps with the first gate electrode with a first insulating layer therebetween and overlaps with the second gate electrode with a second insulating layer therebetween, and the second insulating layer is in contact with the first region.

5. The semiconductor device according to claim 1, wherein the first oxide semiconductor layer, the second oxide semiconductor layer, and the third oxide semiconductor layer include at least one selected from the group consisting of indium, gallium, and zinc.

6. The semiconductor device according to claim 1, wherein the first gate electrode and the second gate electrode have the same potential.

7. The semiconductor device according to claim 1, wherein the first gate electrode and the second gate electrode have different potentials.

8. A semiconductor device comprising:

a first thin film transistor including a first oxide semiconductor layer; and

a second thin film transistor including a second oxide semiconductor layer,

wherein the first thin film transistor includes a first gate electrode, the first gate electrode and the first oxide semiconductor layer overlap with each other,

wherein the second thin film transistor includes a second gate electrode and a third gate electrode, the second gate electrode and the third gate electrode overlap with each other with the second oxide semiconductor layer interposed therebetween,

wherein one of a source and a drain electrode of the first thin film transistor is electrically connected to one of a source and a drain electrode of the second thin film transistor,

wherein one of the first gate electrode and the second gate electrode is electrically connected to the one of the source and the drain electrode of the first thin film transistor, and

wherein the first thin film transistor is one of an enhancement type transistor and a depletion type transistor and the second thin film transistor is the other of the enhancement type transistor and the depletion type transistor.

9. The semiconductor device according to claim 8,

wherein the one of the first gate electrode and the second gate electrode is the first gate electrode.

10. The semiconductor device according to claim 8,

wherein the semiconductor device is a display device.

11. The semiconductor device according to claim 8, wherein the first oxide semiconductor layer and the second oxide semiconductor layer include at least one selected from the group consisting of indium, gallium, and zinc.

12. The semiconductor device according to claim 8, wherein the second gate electrode and the third gate electrode have the same potential.

13. The semiconductor device according to claim 8, wherein the second gate electrode and the third gate electrode have different potentials.

14. The semiconductor device according to claim 8, wherein the first thin film transistor and the second thin film transistor are n-channel thin film transistors.

15. The semiconductor device according to claim 8,

wherein the second oxide semiconductor layer has a first region and a second region,

wherein the second region overlaps with the source or the drain electrode of the second thin film transistor, and

wherein a thickness of the first region is smaller than a thickness of the second region.

16. The semiconductor device according to claim 15, wherein the second oxide semiconductor layer overlaps with the second gate electrode with a first insulating layer therebetween and overlaps with the third gate electrode with a second insulating layer therebetween, and the second insulating layer is in contact with the first region of the second oxide semiconductor layer.

17. A semiconductor device comprising:

a first thin film transistor including a first oxide semiconductor layer; and

a second thin film transistor including a second oxide semiconductor layer,

wherein the first thin film transistor includes a first gate electrode below the first oxide semiconductor layer,

wherein the second thin film transistor includes a second gate electrode below the second oxide semiconductor layer and a third gate electrode above the second oxide semiconductor layer,

wherein one of a source and a drain electrode of the first thin film transistor is electrically connected to one of a source and a drain electrode of the second thin film transistor,

wherein one of the first gate electrode and the second gate electrode is electrically connected to the one of the source and the drain electrode of the first thin film transistor, and

wherein the first thin film transistor is one of an enhancement type transistor and a depletion type transistor and the second thin film transistor is the other of the enhancement type transistor and the depletion type transistor.

18. The semiconductor device according to claim 17,

wherein the one of the first gate electrode and the second gate electrode is the first gate electrode.

19. The semiconductor device according to claim 17,

wherein the semiconductor device is a display device.

20. The semiconductor device according to claim 17, wherein the first oxide semiconductor layer and the second oxide semiconductor layer include at least one selected from the group consisting of indium, gallium, and zinc.

21. The semiconductor device according to claim 17, wherein the second gate electrode and the third gate electrode have the same potential.

22. The semiconductor device according to claim 17, wherein the second gate electrode and the third gate electrode have different potentials.

23. The semiconductor device according to claim 17, wherein the first thin film transistor and the second thin film transistor are n-channel thin film transistors.

24. The semiconductor device according to claim 17,

wherein the second oxide semiconductor layer has a first region and a second region,

wherein the second region overlaps with the source or the drain electrode of the second thin film transistor, and

wherein a thickness of the first region is smaller than a thickness of the second region.

25. The semiconductor device according to claim 24, wherein the second oxide semiconductor layer overlaps with the second gate electrode with a first insulating layer therebetween and overlaps with the third gate electrode with a second insulating layer therebetween, and the second insulating layer is in contact with the first region of the second oxide semiconductor layer.

26. A semiconductor device comprising:

an inverter circuit comprising;

a first thin film transistor; and

a second thin film transistor,

wherein each of the first thin film transistor and the second thin film transistor includes an oxide semiconductor layer and a first gate electrode, the oxide semiconductor layer and the first gate electrode overlap with each other,

wherein only one of the first thin film transistor and the second thin film transistor further includes a second gate electrode,

wherein the oxide semiconductor layer of the only one of the first thin film transistor and the second thin film transistor is interposed between the first gate electrode of the only one of the first thin film transistor and the second thin film transistor and the second gate electrode,

wherein one of a source and a drain electrode of the first thin film transistor is electrically connected to one of a source and a drain electrode of the second thin film transistor, and

wherein the first gate electrode of the first thin film transistor is electrically connected to the one of the source and the drain electrode of the first thin film transistor.

27. The semiconductor device according to claim 26,

wherein the only one of the first thin film transistor and the second thin film transistor is the second thin film transistor.

28. The semiconductor device according to claim 26,

wherein the other of the source and the drain electrode of the only one of the first thin film transistor and the second thin film transistor is electrically connected to a Vss, and the other of the source and the drain electrode of the other of the first thin film transistor and the second thin film transistor is electrically connected to a Vdd.

29. The semiconductor device according to claim 26,

wherein the semiconductor device is a display device.

30. The semiconductor device according to claim 26, wherein the oxide semiconductor layer of the first thin film transistor and the second thin film transistor include at least one selected from the group consisting of indium, gallium, and zinc.

31. The semiconductor device according to claim 26, wherein the first gate electrode of the only one of the first thin film transistor and the second thin film transistor and the second gate electrode have the same potential.

32. The semiconductor device according to claim 26, wherein the first gate electrode of the only one of the first thin film transistor and the second thin film transistor and the second gate electrode have different potentials.

33. The semiconductor device according to claim 26, wherein the first thin film transistor and the second thin film transistor are n-channel thin film transistors.

34. The semiconductor device according to claim 26,

wherein the oxide semiconductor layer of the second thin film transistor has a first region and a second region,

wherein the second region overlaps with the source or the drain electrode of the second thin film transistor, and

wherein a thickness of the first region is smaller than a thickness of the second region.

35. The semiconductor device according to claim 34,

wherein the only one of the first thin film transistor and the second thin film transistor is the second thin film transistor, and

wherein the oxide semiconductor layer of the second thin film transistor overlaps with the first gate electrode of the second thin film transistor with a first insulating layer therebetween and overlaps with the second gate electrode with a second insulating layer therebetween, and the second insulating layer is in contact with the first region of the oxide semiconductor layer of the second thin film transistor.

36. A semiconductor device comprising:

an inverter circuit comprising;

a first thin film transistor; and

a second thin film transistor,

wherein each of the first thin film transistor and the second thin film transistor includes an oxide semiconductor layer and a first gate electrode, the first gate electrode is provided below the oxide semiconductor layer,

wherein only one of the first thin film transistor and the second thin film transistor further includes a second gate electrode over the oxide semiconductor layer of the only one of the first thin film transistor and the second thin film transistor,

wherein one of a source and a drain electrode of the first thin film transistor is electrically connected to one of a source and a drain electrode of the second thin film transistor, and

wherein the first gate electrode of the first thin film transistor is electrically connected to the one of the source and the drain electrode of the first thin film transistor.

37. The semiconductor device according to claim 36,

wherein the only one of the first thin film transistor and the second thin film transistor is the second thin film transistor.

38. The semiconductor device according to claim 36,

wherein the other of the source and the drain electrode of the only one of the first thin film transistor and the second thin film transistor is electrically connected to a Vss, and the other of the source and the drain electrode of the other of the first thin film transistor and the second thin film transistor is electrically connected to a Vdd.

39. The semiconductor device according to claim 36,

wherein the semiconductor device is a display device.

40. The semiconductor device according to claim 36, wherein the oxide semiconductor layers of the first thin film transistor and the second thin film transistor include at least one selected from the group consisting of indium, gallium, and zinc.

41. The semiconductor device according to claim 36, wherein the first gate electrode of the only one of the first thin film transistor and the second thin film transistor and the second gate electrode have the same potential.

42. The semiconductor device according to claim 36, wherein the first gate electrode of the only one of the first thin film transistor and the second thin film transistor and the second gate electrode have different potentials.

43. The semiconductor device according to claim 36, wherein the first thin film transistor and the second thin film transistor are n-channel thin film transistors.

44. The semiconductor device according to claim 36,

wherein the oxide semiconductor layer of the second thin film transistor has a first region and a second region,

wherein the second region overlaps with the source or the drain electrode of the second thin film transistor, and

wherein a thickness of the first region is smaller than a thickness of the second region.

45. The semiconductor device according to claim 44,

wherein the only one of the first thin film transistor and the second thin film transistor is the second thin film transistor, and

wherein the oxide semiconductor layer of the second thin film transistor overlaps with the first gate electrode with a first insulating layer therebetween and overlaps with the second gate electrode with a second insulating layer therebetween, and the second insulating layer is in contact with the first region of the oxide semiconductor layer of the second thin film transistor.