Super-junction trench MOSFET with resurf step oxide and the method to make the same

• US 8,067,800 B2
• Filed: 12/28/2009
• Issued: 11/29/2011
• Est. Priority Date: 12/28/2009
• Status: Active Grant

• Current Assignee: Force Mos Technology Co., Ltd.
• Original Assignee: Force Mos Technology Co., Ltd.
• Inventors: Hsieh, Fu-Yuan
• Primary Examiner(s): Sefer; A.
• Assistant Examiner(s): Harrison; Monica D
• Application Number:
  US12/654,637
• Publication Number:
  US 20110156139A1
• Time in Patent Office: 701 Days
• Field of Search: 257/331, 257/339, 257/E21.41, 257/E29.256, 438/270
• US Class Current: 257/331
• CPC Class Codes: H01L 21/26586 characterised by the angle between the ion beam and the crystal planes or the main crystal surface
• CPC Class Codes: H01L 29/0619 with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
• CPC Class Codes: H01L 29/0634 Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
• CPC Class Codes: H01L 29/0878 Impurity concentration or distribution
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/42368 the thickness being non-uniform
• CPC Class Codes: H01L 29/42376 characterised by the length or the sectional shape
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

A super-junction trench MOSFET with Resurf Stepped Oxide is disclosed. The inventive structure can apply additional freedom for better optimization and manufacturing capability by tuning thick oxide thickness to minimize influence of charge imbalance, trapped charges, etc. . . . . Furthermore, the fabrication method can be implemented more reliably with lower cost.

Claims

1. A super-junction trench MOSFET with resurf stepped oxide, comprising:

a substrate of a first conductivity type;

an epitaxial layer of said first conductivity type grown on said substrate, said epitaxial layer having a lower doping concentration than said substrate;

a plurality of trenches starting from the upper surface of said epitaxial layer and down extending into said epitaxial layer;

a first insulation layer along the inner surface of lower portion of each of said trenches;

a plurality of source electrodes within lower portion of said trenches and surrounded with said first insulation layer;

a second insulation layer along the inner surface of upper portion of each of said trenches and along the top surface of said first insulation layer and said source electrodes, said second insulation layer has a thinner thickness than said first insulation layer;

a plurality of gate electrodes within upper portion of said trenches and surrounded with said second insulation layer;

a plurality of first doped column regions of said first conductivity type with column shape within said epitaxial layer, each of said first doped column regions formed adjacent to the sidewalls of said trenches and having column bottom above trench bottom of said trenches;

a plurality of second doped column regions of a second conductivity type with column shape within said epitaxial layer, each of said second doped column regions formed in parallel surrounded with said first doped column regions;

a plurality of body regions of said second conductivity type within said epitaxial layer, each of said body regions formed adjacent to the upper sidewalls of said trenches and onto the top surface of said first doped column regions and said second doped column regions; and

a plurality of source regions of said first conductivity type near the top surface of said body region and adjacent to the upper sidewalls of said trenches, said source region has a higher doping concentration than said epitaxial layer.

2. The MOSFET of claim 1, wherein said trench bottom of said trenches is above said substrate.

3. The MOSFET of claim 1, wherein each of said trenches further extends into said substrate.

4. The MOSFET of claim 1 further comprises a plurality of avalanche enhancement doped regions of said second conductivity type within said body regions and below said source regions, each of said avalanche enhancement doped regions formed between a pair of said source regions and having a higher doping concentration than said body regions;

and a plurality of shallow contact doped regions of said second conductivity type near the top surface of said body regions, each of said shallow contact doped regions formed between a pair of said source regions and onto said avalanche enhancement doped regions, said shallow contact doped regions having a higher doping concentration than said avalanche enhancement doped regions.

5. The MOSFET of claim 1 further comprises Guard Ring as termination area when breakdown voltage is less than or equal to 100V.

6. The MOSFET of claim 1 further comprises Guard Ring and multiple floating rings as termination area when breakdown voltage is larger than 100V.

7. The MOSFET of claim 1 further comprises source metal onto a third insulation layer and extend into contact regions between every two adjacent said third insulation layer to contact with said shallow contact doped regions and said source regions in active area or only shallow contact doped regions near by termination area.

8. A super-junction trench MOSFET with resurf stepped oxide, comprising:

a substrate of a first conductivity type;

an epitaxial layer of said first conductivity type grown on said substrate, said epitaxial layer having a lower doping concentration than said substrate;

a plurality of trenches starting from the upper surface of said epitaxial layer and down extending into said epitaxial layer;

a first insulation layer along the inner surface of lower portion of each of said trenches;

a second insulation layer along the inner surface of upper portion of each of said trenches, said second insulation layer has a thinner thickness than said first insulation layer;

a plurality of gate electrodes within said trenches surrounded with said first insulation layer and said second insulation layer;

a plurality of first doped column regions of said first conductivity type within said epitaxial layer, each of said first doped regions column formed adjacent to the sidewalls of said trenches and having column bottom above trench bottom of said trenches;

a plurality of a second doped column regions of a second conductivity type within said epitaxial layer, each of said second doped column regions formed in parallel surrounded with said first doped column regions;

a plurality of body regions of said second conductivity type within said epitaxial layer, each of said body regions formed adjacent to the upper sidewalls of said trenches and onto the top surface of said first doped column regions and said second doped column regions; and

a plurality of source regions of said first conductivity type near the top surface of said body regions and adjacent to the upper sidewalls of said trenches, said source regions have a higher doping concentration than said epitaxial layer.

9. The MOSFET of claim 8, wherein said trench bottom of said trenches is above said substrate.

10. The MOSFET of claim 8, wherein each of said trenches further extends into said substrate.

11. The MOSFET of claim 8 further comprises a plurality of avalanche enhancement doped regions of said second conductivity type within said body regions and below said source regions, each of said avalanche enhancement doped regions formed between a pair of said source regions and having a higher doping concentration than said body regions;

and a plurality of shallow contact doped regions of said second conductivity type near the top surface of said body regions, each of said shallow contact doped regions formed between a pair of said source regions and onto said avalanche enhancement doped regions, said shallow contact doped regions having a higher doping concentration than said avalanche enhancement doped regions.

12. The MOSFET of claim 8 further comprises Guard Ring as termination area when breakdown voltage is less than or equal to 100V.

13. The MOSFET of claim 8 further comprises Guard Ring and multiple floating rings as termination area when breakdown voltage is larger than 100V.

14. The MOSFET of claim 8 further comprises source metal onto a third insulation layer and extend into contact regions between every two adjacent said third insulation layer to contact with said shallow contact doped regions and said source regions in active area or only shallow contact doped regions near by termination area.

15. A Method for manufacturing a super-junction trench MOSFET comprising the steps of:

growing an epitaxial layer of a first conductivity type upon a heavily doped substrate of a first conductivity type;

applying a trench mask to form a plurality of trenches by etching through said oxide layer, and into said epitaxial layer or through said epitaxial layer and into said substrate by successively dry oxide etch and dry silicon etch;

growing a sacrificial oxide layer onto inner surface of said trenches and removing said sacrificial oxide to remove the plasma damage;

growing a screen oxide along the inner surface of said trenches;

carrying out angle Ion Implantation of first conductivity type dopant and diffusion to form the first doped column regions between two adjacent sidewalls of said trenches;

carrying out angle Ion Implantation of second conductivity type dopant and diffusion to form the second doped column regions adjacent to the sidewalls of said trenches and in parallel surrounding said first doped column regions;

forming a first insulation layer along the inner surface of said trenches by thermal oxide growth or oxide deposition;

depositing first doped polysilicon filling said trenches and close to said insulation layer serving as source electrodes;

etching back said source electrodes and said first insulation layer from the upper portion of said trenches and from the top surface of said epitaxial layer;

growing a second insulation layer along the upper sidewalls of each of said trenches and onto the top surface of said source electrodes and said first insulation layer, said second insulation layer has a thinner thickness than said first insulation layer;

depositing second doped polysilicon filling the upper portion of said trenches and close to said second insulation layer to serving as gate electrodes;

etching back said gate electrodes by CMP (Chemical Mechanical Polishing) or Plasma Etch;

applying a body mask onto top surface of said epitaxial layer;

carrying out Ion Implantation of second conductivity type dopant and diffusion to form body region;

removing said body mask and applying a source mask onto top surface of said epitaxial layer;

carrying out Ion Implantation of first conductivity type dopant and diffusion to form source region; and

removing said source mask and depositing a third insulation layer onto top surface of said epitaxial layer.

16. The method of claim 15 further comprises applying a contact mask onto top surface of said third insulation layer and etching contact holes by dry oxide etch to form contact regions;

carrying out high energy Ion Implantation of second conductivity type dopant to form the avalanche enhancement doped regions; and

carrying out blank Ion Implantation of second conductivity type dopant to form the shallow contact doped regions.

17. The method of claim 15 further comprises applying Guard Ring mask and carrying out Ion Implantation of second conductivity type dopant and diffusion to form Guard Ring before applying the body mask.

18. The method of claim 15 further comprises depositing metal layer onto top surface of third insulation layer and applying metal mask continued by etching metal layer to form source metal.