Nonplanar device with thinned lower body portion and method of fabrication

• US 8,067,818 B2
• Filed: 11/24/2010
• Issued: 11/29/2011
• Est. Priority Date: 10/25/2004
• Status: Expired due to Fees

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Shah, Uday, Chau, Robert S., Letson, Thomas A., Brask, Justin K., Doyle, Brian
• Primary Examiner(s): Smith; Bradley K
• Assistant Examiner(s): Movva; Amar
• Application Number:
  US12/954,241
• Publication Number:
  US 20110062512A1
• Time in Patent Office: 370 Days
• Field of Search: 257/618, 257/E29.259
• US Class Current: 257/618
• CPC Class Codes: H01L 21/823431 with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 21/845 including field-effect transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 27/0886 including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 27/1211 combined with field-effect transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/42384 for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/66818 the channel being thinned after patterning, e.g. sacrificial oxidation on fin
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/7853 the body having a non-rectangular crossection
• CPC Class Codes: H01L 29/7854 with rounded corners
• CPC Class Codes: H01L 29/7856 with an non-uniform gate, e.g. varying doping structure, shape or composition on different sides of the fin, or different gate insulator thickness or composition on opposing fin sides H01L29/7855 takes precedence
• CPC Class Codes: H01L 2924/13067 FinFET, source/drain region shapes fins on the silicon surface
• CPC Class Codes: Y10S 438/978 forming tapered edges on substrate or adjacent layers

Abstract

A nonplanar semiconductor device having a semiconductor body formed on an insulating layer of a substrate. The semiconductor body has a top surface opposite a bottom surface formed on the insulating layer and a pair of laterally opposite sidewalls wherein the distance between the laterally opposite sidewalls at the top surface is greater than at the bottom surface. A gate dielectric layer is formed on the top surface of the semiconductor body and on the sidewalls of the semiconductor body. A gate electrode is formed on the gate dielectric layer on the top surface and sidewalls of the semiconductor body. A pair of source/drain regions are formed in the semiconductor body on opposite sides of the gate electrode.

Claims

1. A semiconductor device comprising:

a semiconductor body formed on an insulating layer of a substrate, said semiconductor body having a top surface opposite a bottom surface formed on said insulating layer and a pair of laterally opposite sidewalls extending between said top surface and said bottom surface wherein the laterally opposite sidewalls include a tapered portion that extends from the top surface to the bottom surface of the semiconductor body such that the distance between said laterally opposite sidewalls at said top surface is greater than at said bottom surface;

a gate dielectric layer formed on and in direct contact with said top surface and said sidewalls of said semiconductor body from said top surface to said bottom surface;

a gate electrode formed on said gate dielectric layer on said top surface and sidewalls of said semiconductor body; and

a pair of source/drain region formed in said semiconductor body on opposite sides of said gate electrode.

2. The semiconductor device of claim 1 wherein said distance between said sidewalls at the bottom surface of said semiconductor body is approximately ½

to ⅔

of the distance between said sidewalls at the top surface of said semiconductor body.

3. The semiconductor device of claim 1 wherein the distance between said sidewalls at the bottom portion of said semiconductor body is made sufficiently small so as to improve the short channel effects of said transistor.

4. The semiconductor device of claim 1 wherein the distance between said laterally opposite sidewalls at said top surface of said semiconductor body is approximately 20-30 nm.

5. The semiconductor device of claim 1 wherein the distance between said laterally opposite sidewalls near said bottom portion of said semiconductor body is approximately 10-15 nm.

6. The semiconductor device of claim 1 wherein the tapered portion that extends from the top surface to the bottom surface of the semiconductor body is a facet.

7. The semiconductor device of claim 1 wherein said semiconductor body comprises silicon.

8. The semiconductor device of claim 1 wherein the distance between said sidewalls near the bottom surface of said semiconductor body is approximately 50-66% of the distance between said sidewalls at the top of said semiconductor body.

9. The semiconductor device of claim 1 wherein the composition of said gate dielectric layer formed on said top surface is the same composition as said gate dielectric layer formed on said sidewalls.

10. The semiconductor device of claim 1 wherein said gate dielectric layer is a continuous gate dielectric layer formed on and in direct contact with said top surface and said sidewalls of said semiconductor body.