Flat semiconductor package with half package molding

• US 8,067,821 B1
• Filed: 04/10/2008
• Issued: 11/29/2011
• Est. Priority Date: 04/10/2008
• Status: Active Grant

• Current Assignee: Amkor Technology Singapore Holding Pte., Ltd. (Amkor Technology Incorporated)
• Original Assignee: Amkor Technology Incorporated
• Inventors: Olson, Timothy L., Choi, YeonHo
• Primary Examiner(s): Nguyen; Cuong Q
• Assistant Examiner(s): Lam; Cathy N
• Application Number:
  US12/100,886
• Time in Patent Office: 1,328 Days
• Field of Search: 257/666, 257/676, 257/784, 257/E23.037, 257/E23.046, 257/671, 257/777
• US Class Current: 257/666
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/32245 the item being metallic
• CPC Class Codes: H01L 2224/32257 the layer connector connecting to a bonding area disposed in a recess of the surface of the item
• CPC Class Codes: H01L 2224/45015 being circular
• CPC Class Codes: H01L 2224/45124 Aluminium (Al) as principal constituent
• CPC Class Codes: H01L 2224/45139 Silver (Ag) as principal constituent
• CPC Class Codes: H01L 2224/45144 Gold (Au) as principal constituent
• CPC Class Codes: H01L 2224/45147 Copper (Cu) as principal constituent
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48137 the bodies being arranged next to each other, e.g. on a common substrate
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/48247 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/48465 the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
• CPC Class Codes: H01L 2224/49109 outside the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/49171 Fan-out arrangements
• CPC Class Codes: H01L 2224/73265 Layer and wire connectors
• CPC Class Codes: H01L 2225/1029 the support being a lead frame
• CPC Class Codes: H01L 2225/1041 Special adaptations for top connections of the lowermost container, e.g. redistribution layer, integral interposer
• CPC Class Codes: H01L 2225/1058 Bump or bump-like electrical connections, e.g. balls, pillars, posts
• CPC Class Codes: H01L 23/3107 the device being completely enclosed
• CPC Class Codes: H01L 23/49541 : Geometry of the lead-frame
• CPC Class Codes: H01L 23/49551 : characterised by bent parts
• CPC Class Codes: H01L 24/45 : of an individual wire connector
• CPC Class Codes: H01L 24/48 : of an individual wire connector
• CPC Class Codes: H01L 24/49 : of a plurality of wire connectors
• CPC Class Codes: H01L 24/73 : Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
• CPC Class Codes: H01L 25/03 : all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
• CPC Class Codes: H01L 25/105 : the devices being of a type provided for in group H01L27/00
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01047 : Silver [Ag]
• CPC Class Codes: H01L 2924/01075 : Rhenium [Re]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/207 : Diameter ranges

Abstract

In accordance with the present invention, there are provided multiple embodiments of a semiconductor package, each embodiment including a uniquely configured leadframe sized and configured to maximize the available number of exposed leads in the semiconductor package. More particularly, each embodiment of the semiconductor package of the present invention includes a generally planar die paddle defining multiple peripheral edge segments and a plurality of leads, the exposed portions of the bottom surfaces of which are segregated into at least two concentric rows. Connected to the top surface of the die paddle is at least one semiconductor die which is electrically connected to at least some of the leads of each row. At least portions of the die paddle, the leads, and the semiconductor die are encapsulated by a package body, the bottom surfaces of the die paddle and the leads of both rows thereof being exposed in a common exterior surface of the package body. In certain embodiments of the present invention, the top surfaces of at least some of leads of the leadframe are also exposed in an exterior surface of the package body.

Claims

1. A semiconductor package comprising:

a generally planar die paddle defining multiple peripheral edge segments;

a plurality of first leads segregated into at least two sets which extend along respective ones of at least two peripheral edge segments of the die paddle;

a plurality of second leads which each include first and second downsets formed therein in spaced relation to each other, the second leads being segregated into at least two sets which extend along respective ones of at least two peripheral edge segments of the die paddle;

a plurality of third leads, at least some of which include a downset formed therein, the third leads being segregated into at least two sets which extend along respective ones of at least two peripheral edge segments of the die paddle;

a semiconductor die attached to the die paddle and electrically connected to at least one of each of the first second and third leads; and

a package body defining opposed, generally planar top and bottom surfaces and multiple side surfaces, the package body at least partially encapsulating the first, second and third leads and the semiconductor die such that the first and second downsets of the second leads and the downsets of the third leads are covered by the package body, at least portions of the die paddle and the first and second leads are exposed in and substantially flush with the bottom surface of the package body, and at least portions of the second and third leads are exposed in and substantially flush with the top surface of the package body.

2. The semiconductor package of claim 1 wherein at least some of the first leads are formed to include an enlarged locking tip structure to facilitate the anchoring thereof to the package body.

3. The semiconductor package of claim 1 wherein the die paddle has a generally quadrangular configuration, and the first, second and third leads are segregated into at least four sets which each extend along a respective one of the peripheral edge segments of the die paddle.

4. The semiconductor package of claim 1 wherein the semiconductor die is electrically connected to the first, second and third leads by conductive wires which are covered by the package body.

5. The semiconductor package of claim 4 wherein:

each of the first leads defines a terminal which is exposed in the bottom surface of the package body;

each of the second leads includes an inner end portion, a wire bond zone, and an outer end portion, the inner end portion being disposed between the first downset thereof and the die paddle and defining a terminal which is exposed in the bottom surface of the package body, the first downset extending, between the inner end portion and the wire bond zone thereof, and the second downset extending between the wire bond zone and the outer end portion thereof;

each of the third leads includes a wire bond zone and an outer end portion, the downset of each of the third leads extending between the wire bond zone and the outer end portion thereof; and

the conductive wires extend from the semiconductor die to respective ones of the first leads and the wire bond zones of the second leads and third leads.

6. The semiconductor package of claim 5 wherein the outer end portions of the second and third leads each define a terminal which is exposed in the top surface of the package body.

7. The semiconductor package of claim 5 wherein:

the die paddle, the first leads and the inner end portions of the second leads extend along a first plane;

the wire bond zones of the second and third leads each extend along a second plane which is disposed in spaced, generally parallel relation to the first plane; and

the outer end portions of the second and third leads each extend along a third plane which is disposed in spaced, generally parallel relation to the second plane such that the second plane extends between the first and third planes.

8. The semiconductor package of claim 5 wherein portions of the outer end portions of the third leads protrude from respective ones of the side surfaces of the package body and are bent to assume a gull-wing configuration.

9. The semiconductor package of claim 5 wherein the terminals defined by the first leads are offset relative to the terminals defined by the second leads.

10. A semiconductor package comprising:

a die paddle;

a plurality of second leads which each include first and second downsets formed therein in spaced relation to each other, the second leads extending along the die paddle;

a plurality of third leads, at least some of which include a downset formed therein, the third leads extending along the die paddle;

a semiconductor die attached to the die paddle and electrically connected to at least one of each of the first, second and third leads; and

a package body defining opposed top and bottom surfaces and multiple side surfaces, the package body at least partially encapsulating the second and third leads and the semiconductor die such that the first and second downsets of the second leads and the downsets of the third leads are covered by the package body, at least portions of the die paddle and the second leads are exposed in the bottom surface of the package body, and at least portions of the second and third leads are exposed in the top surface of the package body.

11. The semiconductor package of claim 10 wherein:

each of the second leads includes an inner end portion, a wire bond zone, and an outer end portion, the inner end portion being disposed between the first downset thereof and the die paddle and defining a terminal which is exposed in the bottom surface of the package body, the first downset extending between the inner end portion and the wire bond zone thereof, the second downset extending between the wire bond zone and the outer end portion thereof, and the outer end portion defining a terminal which is exposed in the top surface of the package body;

each of the third leads includes a wire bond zone and an outer end portion, the downset of each of the third leads extending between the wire bond zone and the outer end portion thereof, and the outer end portion defining a terminal which is exposed in the top surface of the package body; and

conductive wires extend from the semiconductor die to respective ones of the wire bond zones of the second leads and third leads.

12. The semiconductor package of claim 11 wherein portions of the outer end portions of the third leads protrude from respective ones of the side surfaces of the package body and are bent to assume a gull-wing configuration.

13. The semiconductor package of claim 11 further comprising a plurality of first leads extending along the die paddle, the semiconductor die being electrically connected to at least one of the first leads and the package body at least partially encapsulating the first leads such that each of the first leads defines a terminal which is exposed in the bottom surface of the package body.

14. A semiconductor package comprising:

a die paddle;

a plurality of second leads which each include first and second downsets formed therein and define a wire bond zone between the first and second downsets, the second leads extending along the die paddle;

a plurality of third leads, at least some of which include a downset formed therein, the third leads extending along the die paddle and each defining a wire bond zone between the downset thereof and the die paddle;

a semiconductor die attached to the die paddle and electrically connected to at least one of each of the second and third leads; and

a package body defining opposed top and bottom surfaces, the package body at least partially encapsulating the second and third leads and the semiconductor die such that the first and second downsets of the second leads and the downsets of the third leads are covered by the package body, at least portions of the die paddle and the second leads are exposed in the bottom surface of the package body, and at least portions of the second and third leads are exposed in the top surface of the package body.