Low-distortion voltage variable capacitor assemblies
First Claim
1. An apparatus that receives a signal voltage, the apparatus comprising:
- a capacitive network that includes a first half cell connected in parallel with a second half cell,wherein the first half cell comprises a circuit with two or more voltage variable capacitors (VVCs) configured in anti-series in which a first VVC of said two or more VVCs with a same bias voltage orientation as the signal voltage associated with said apparatus assumes one capacitance and a second VVC of said two or more VVCs with an opposite bias voltage orientation as the signal voltage assumes another capacitance, andwherein the second half cell comprises a circuit with two or more VVCs configured in anti-series in which a third VVC of said two or more VVCs with the same bias voltage orientation as the signal voltage associated with said apparatus assumes the same values as said anti-oriented VVCs in said first half cell and a fourth VVC with the opposite bias voltage orientation as the signal voltage assumes the same values as said like-oriented VVCs in said first half cell;
a first Direct Current (DC) feed connected between the first VVC and the second VVC; and
a second DC feed connected between the third VVC and the fourth VVC,wherein said VVCs are voltage tunable dielectric capacitors,wherein values for the voltage tunable dielectric capacitors are selected based on reducing an error function over a desired range of bias and signal voltages as a function of a capacitance-voltage curve that numerically models the voltage tunable dielectric capacitors, andwherein the error function is based on a change in a net capacitance of the capacitive network.
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Abstract
An embodiment of the present invention provides an apparatus, comprising a first half cell comprising a circuit with two or more voltage variable capacitors (VVCs) configured in anti-series in which one or more of the two or more VVCs with the same bias voltage orientation as a signal voltage associated with the apparatus assume one capacitance and one or more of the two or more VVCs with the opposite bias voltage orientation as the signal voltage assume another capacitance, and a second half cell connected in parallel to the first half cell, comprising a circuit with two or more VVCs configured in anti series in which one or more of the two or more VVCs with the same bias voltage orientation as a signal voltage associated with the apparatus assume the same values as the anti-oriented VVCs in the first half cell and a one or more VVCs with the opposite bias voltage orientation as a signal voltage assume the same values as the like oriented VVCs in the first half cell.
135 Citations
20 Claims
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1. An apparatus that receives a signal voltage, the apparatus comprising:
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a capacitive network that includes a first half cell connected in parallel with a second half cell, wherein the first half cell comprises a circuit with two or more voltage variable capacitors (VVCs) configured in anti-series in which a first VVC of said two or more VVCs with a same bias voltage orientation as the signal voltage associated with said apparatus assumes one capacitance and a second VVC of said two or more VVCs with an opposite bias voltage orientation as the signal voltage assumes another capacitance, and wherein the second half cell comprises a circuit with two or more VVCs configured in anti-series in which a third VVC of said two or more VVCs with the same bias voltage orientation as the signal voltage associated with said apparatus assumes the same values as said anti-oriented VVCs in said first half cell and a fourth VVC with the opposite bias voltage orientation as the signal voltage assumes the same values as said like-oriented VVCs in said first half cell; a first Direct Current (DC) feed connected between the first VVC and the second VVC; and a second DC feed connected between the third VVC and the fourth VVC, wherein said VVCs are voltage tunable dielectric capacitors, wherein values for the voltage tunable dielectric capacitors are selected based on reducing an error function over a desired range of bias and signal voltages as a function of a capacitance-voltage curve that numerically models the voltage tunable dielectric capacitors, and wherein the error function is based on a change in a net capacitance of the capacitive network. - View Dependent Claims (2)
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3. An apparatus that receives a signal voltage, the apparatus comprising:
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a capacitive network that includes a first half cell connected in parallel with a second half cell, wherein the first half cell comprises a circuit with two or more voltage variable capacitors (VVCs) configured in anti-series in which a first VVC of said two or more VVCs with a same bias voltage orientation as the signal voltage associated with said apparatus assumes one capacitance and a second VVC of said two or more VVCs with an opposite bias voltage orientation as the signal voltage assumes another capacitance, and wherein the second half cell comprises a circuit with two or more VVCs configured in anti-series in which a third VVC of said two or more VVCs with the same bias voltage orientation as the signal voltage associated with said apparatus assumes the same values as said anti-oriented VVCs in said first half cell and a fourth VVC with the opposite bias voltage orientation as the signal voltage assumes the same values as said like-oriented VVCs in said first half cell; a first Direct Current (DC) feed connected between the first VVC and the second VVC; and a second DC feed connected between the third VVC and the fourth VVC, wherein said apparatus is adapted to allow for a desired total capacitance minimally dependent of said signal voltage by setting a required bias voltage, wherein values for the VVCs are selected based on reducing an error function over a desired range of the received signal voltage as a function of a capacitance-voltage curve associated with the VVCs, and wherein the error function is based on a change in a net capacitance of the capacitive network. - View Dependent Claims (4, 5, 6, 7, 8, 9)
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10. A method comprising:
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selecting using a processor, a numerical model for a tunable capacitive network, wherein the tunable capacitive network comprises a first half cell connected in parallel with a second half cell, wherein the first half cell includes a first circuit having first and second voltage variable capacitors (VVCs) configured in anti-series in which the first VVC with a same bias voltage orientation as a received signal voltage assumes a first capacitance and the second VVC with an opposite bias voltage orientation as the received signal voltage assumes a second capacitance, and wherein the second half cell includes a second circuit having third and fourth VVCs configured in anti-series in which the third VVC with the same bias voltage orientation as the received signal voltage assumes the second capacitance and the fourth VVC with the opposite bias voltage orientation as the received signal voltage assumes the first capacitance, wherein a first Direct Current (DC) feed is connected between the first VVC and the second VVC, and wherein a second DC feed is connected between the third VVC and the fourth VVC; selecting using the processor, an error function based on a change in a net capacitance of the tunable capacitive network or its reciprocal as a function of the numerical model, a signal voltage associated with the tunable capacitive network and a bias voltage associated with the tunable capacitive network; and selecting capacitance values for the tunable capacitive network using the processor, to reduce the error function over a desired range of the bias and signal voltages as a function of the numerical model. - View Dependent Claims (11, 12, 13, 14, 15, 16, 17, 18, 19, 20)
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Specification