Input/output multiplexer bus
First Claim
Patent Images
1. An apparatus, comprising:
- a plurality of input/output (“
I/O”
) ports;
measurement circuitry to measure one or more electrical properties of one or more devices to be externally coupled to one or more of the I/O ports; and
a I/O multiplexer bus coupled between the I/O ports and the measurement circuitry, the I/O multiplexer bus programmable to selectively couple the measurement circuitry to any of the I/O ports, wherein the I/O multiplexer bus includes;
a bus line coupled to the measurement circuitry;
a plurality of bus line switches, each coupled between one of the I/O ports and the bus line; and
switching logic coupled to the bus line switches to control the bus line switches; and
a current source coupled to the bus line to drive a current through the bus line, wherein the switching logic is coupled to selectively drive the current through one or more of the I/O ports.
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Abstract
An input/output (“I/O”) system includes a plurality of input/output (“I/O”) ports, measurement circuitry, and an I/O multiplexer bus. The measurement circuitry is coupled to measure one or more electrical properties of one or more devices to be externally coupled to one or more of the I/O ports. The I/O multiplexer bus is coupled between the I/O ports and the measurement circuitry. The I/O multiplexer bus is programmable to selectively couple the measurement circuitry to any of the I/O ports.
1238 Citations
16 Claims
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1. An apparatus, comprising:
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a plurality of input/output (“
I/O”
) ports;measurement circuitry to measure one or more electrical properties of one or more devices to be externally coupled to one or more of the I/O ports; and a I/O multiplexer bus coupled between the I/O ports and the measurement circuitry, the I/O multiplexer bus programmable to selectively couple the measurement circuitry to any of the I/O ports, wherein the I/O multiplexer bus includes; a bus line coupled to the measurement circuitry; a plurality of bus line switches, each coupled between one of the I/O ports and the bus line; and switching logic coupled to the bus line switches to control the bus line switches; and a current source coupled to the bus line to drive a current through the bus line, wherein the switching logic is coupled to selectively drive the current through one or more of the I/O ports. - View Dependent Claims (2, 3, 4, 5, 6, 7)
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8. An apparatus, comprising:
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a plurality of input/output (“
I/O”
) means for conveying analog signals into and out of an integrated circuit;measurement means for measuring one or more electrical properties of one or more devices to be externally coupled to one or more of the I/O means; and means for time-sharing the measurement means across the plurality of I/O means, wherein the means for time-sharing is programmable to selectively individually couple the measurement means to any of the I/O means, wherein the means for time-sharing includes; a voltage line coupled to a means for generating a voltage; a plurality of voltage line switches, each coupled between the voltage line and one of the I/O means; and a means for controlling the voltage line switches to selectively couple the means for generating the voltage to any of the I/O means. - View Dependent Claims (9, 10, 11)
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12. A method, comprising:
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sequentially connecting each one of a plurality of variable capacitance switches of a capacitance sense user interface to a signal source via an input/output (“
I/O”
) multiplexer bus;reciprocally charging and discharging each of the variable capacitance switches through the I/O multiplexer bus; sequentially connecting each one of the plurality of variable capacitance switches to capacitance measurement circuitry via the I/O multiplexer bus to monitor a capacitance of each of the variable capacitance switches; and time sharing the capacitance measurement circuitry across a plurality of I/O ports each coupled to one of the variable capacitance switches to monitor the capacitance of each of the variable capacitance switches by iteratively reprogramming the I/O multiplexer bus under control of a processor. - View Dependent Claims (13, 14, 15, 16)
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Specification