MOS resistor with second or higher order compensation

• US 8,067,975 B2
• Filed: 04/15/2010
• Issued: 11/29/2011
• Est. Priority Date: 10/25/2007
• Status: Expired due to Fees

• Current Assignee: Atmel Corporation (Microchip Technology Incorporated)
• Original Assignee: Atmel Corporation (Microchip Technology Incorporated)
• Inventors: Fort, Jimmy
• Primary Examiner(s): Tra; Quan
• Application Number:
  US12/761,185
• Publication Number:
  US 20100201430A1
• Time in Patent Office: 593 Days
• Field of Search: 327512-513, 327/539, 323/313, 323/315
• US Class Current: 327/513
• CPC Class Codes: G05F 3/30 Regulators using the difference between the base-emitter voltages of two bipolar transistors operating at different current densities G05F3/26 takes precedence
• CPC Class Codes: H01L 27/0802 Resistors only

Abstract

A circuit arrangement (e.g., an integrated circuit) generates a second or higher order compensation voltage to compensate for variations in operation parameters (e.g., temperature and process variations). In one aspect, the compensation voltage is applied to a MOS resistor to compensate for mobility variations of the MOS resistor by maintaining a stable equivalent resistance. The compensated MOS resistor can provide a relatively stable resistance for a variety of analog circuit applications, such as a current reference.

Claims

1. An integrated circuit arrangement, comprising:

a compensation circuit coupled to receive a current proportional to absolute temperature, and operable to use the current to generate a compensation voltage based on an approximation of a variation of mobility of a metal-oxide-semiconductor (MOS) resistor due to absolute temperature variation, the compensation voltage being based on a combination of a first voltage substantially proportional to absolute temperature and a second voltage substantially proportional to absolute temperature squared, the compensation voltage being capable to cause the MOS resistor to operate in a triode region.

2. The integrated circuit arrangement of claim 1, further comprising:

a MOS resistor coupled to the compensation circuit and operable for receiving the compensation voltage.

3. The integrated circuit arrangement of claim 1, further comprising:

a current source coupled to the compensation circuit and operable for generating the current proportional to the absolute temperature.

4. The integrated circuit arrangement of claim 1, further comprising:

a reference circuit coupled to the MOS resistor and operable for providing a reference current or voltage.

5. The integrated circuit arrangement of claim 1, wherein the compensation voltage is generated to be approximately proportional to

6. The integrated circuit arrangement of claim 1, wherein the approximation is a second order or higher approximation.

7. A method of compensating variation of metal-oxide-semiconductor (MOS) resistors, comprising:

receiving a current substantially proportional to absolute temperature; and

generating a compensation voltage using the current, wherein the compensation voltage is based on a second or higher order approximation of a variation of mobility of a metal oxide semiconductor (MOS) resistor due to absolute temperature variation, the compensation voltage being based on a combination of a first voltage substantially proportional to absolute temperature and a second voltage substantially proportional to absolute temperature squared.

8. The method of claim 7, further comprising:

generating the current substantially proportional to the absolute temperature; and

applying the compensation voltage to a MOS resistor.

9. The method of claim 8, further comprising:

generating a current or voltage reference using the MOS resistor.

10. The method of claim 9, further comprising:

generating the compensation voltage to be approximately proportional to

11. A system for compensating variation of metal-oxide-semiconductor (MOS) resistors, comprising:

means for receiving a current substantially proportional to absolute temperature; and

means for generating a compensation voltage using the current, wherein the compensation voltage is based on a second or higher order approximation of a variation of mobility of a metal oxide semiconductor (MOS) resistor due to absolute temperature variation, the compensation voltage being based on a combination of a first voltage substantially proportional to absolute temperature and a second voltage substantially proportional to absolute temperature squared.

12. The system of claim 11, further comprising:

means for generating the current proportional to the absolute temperature.

13. The system of claim 11, further comprising:

means for generating a current or voltage reference using the MOS resistor.