Three dimensional stacked nonvolatile semiconductor memory

• US 8,068,364 B2
• Filed: 11/19/2010
• Issued: 11/29/2011
• Est. Priority Date: 04/23/2008
• Status: Active Grant

• Current Assignee: Kioxia Corporation
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Maejima, Hiroshi
• Primary Examiner(s): AUDUONG, GENE NGHIA
• Application Number:
  US12/950,509
• Publication Number:
  US 20110063910A1
• Time in Patent Office: 375 Days
• Field of Search: 365/185.11, 365/185.05, 365/185.18, 365/185.23, 365/51, 365/63
• US Class Current: 365/185.11
• CPC Class Codes: G11C 16/04 using variable threshold transistors, e.g. FAMOS
• CPC Class Codes: G11C 16/0408 comprising cells containing floating gate transistors G11C16/0483, G11C16/0491 take precedence
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 16/08 Address circuits; Decoders; Word-line control circuits
• CPC Class Codes: G11C 5/02 Disposition of storage elements, e.g. in the form of a matrix array
• CPC Class Codes: G11C 5/063 Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H10B 41/20 characterised by three-dimensional arrangements, e.g. with cells on different height levels
• CPC Class Codes: H10B 41/27 the channels comprising vertical portions, e.g. U-shaped channels
• CPC Class Codes: H10B 41/40 characterised by the peripheral circuit region
• CPC Class Codes: H10B 41/41 of a memory region comprising a cell select transistor, e.g. NAND

Abstract

A three dimensional stacked nonvolatile semiconductor memory according to an example of the present invention includes a memory cell array comprised of first and second blocks disposed side by side in a first direction, and a driver disposed on one end of the memory cell array in a second direction orthogonal to the first direction. First select gate lines in the first block and first select gate lines in the second block are connected to the driver after they are commonly connected in one end in the second direction of the memory cell array in a relation of one to one.

Claims

1. A three dimensional stacked nonvolatile semiconductor memory comprising:

a semiconductor substrate;

a memory cell array comprised of first and second blocks disposed on the semiconductor substrate side by side in a first direction; and

a first driver disposed on one end of the memory cell array in a second direction orthogonal to the first direction,

wherein each of the first and second blocks is comprised of at least three conductive layers stacked on the semiconductor substrate by being insulated from each other, a bit line disposed on the at least three conductive layers by being insulated therefrom, and columnar semiconductors passing through the at least three conductive layers,

wherein an uppermost layer of the at least three conductive layers is comprised of first select gate lines extending in the second direction, a lowermost layer of the at least three conductive layers is a second select gate line, remaining conductive layers excluding the uppermost layer and the lowermost layer of the at least three conductive layers are a word line,

wherein select gate transistors are comprised of the first select gate lines and the columnar semiconductors, and the second select gate line and the columnar semiconductors, respectively, and memory cells are comprised of the word line and the columnar semiconductor, respectively, and a selected first cell unit and non-selected second cell units are connected to the bit line, and each of the selected first cell unit and the non-selected second cell units is comprised of the memory cells and the select gate transistors, and

wherein the first select gate lines in the first block and the first select gate lines in the second block are connected to the first driver after they are commonly connected in one end in the second direction of the memory cell array in a relation of one to one.

2. The memory according to claim 1, wherein the word lines and the second select gate lines in the first and second blocks are connected to the first driver, respectively.

3. The memory according to claim 1, wherein the word lines and the second select gate lines in the first and second blocks are connected to a second driver disposed on the other end in the second direction of the memory cell array, respectively.

4. The memory according to claim 1, wherein an i-th (i is a natural number) first select gate line from the second block side of the first select gate lines in the first block is commonly connected an i-th first select gate line from the first block side of the first select gate lines in the second block.

5. The memory according to claim 1, wherein the memory cell is a MONOS memory cell which stores data by accumulating a charge in insulation films between the word line and the columnar semiconductor.

6. The memory according to claim 1, wherein one end in the second direction of the at least three conductive layers is formed stepwise.

7. The memory according to claim 6, wherein one end in the second direction of each of the at least three conductive layers is connected to an interconnect line located above the at least three conductive layers through a contact plug.

8. The memory according to claim 7, wherein the interconnect line is connected to the first driver.

9. The memory according to claim 6, wherein one end in the second direction of each of the at least three conductive layers excluding the uppermost layer is connected to an interconnect line located above the at least three conductive layers through a contact plug.

10. The memory according to claim 9, wherein the interconnect line is connected to the first driver.

11. The memory according to claim 9, wherein the other end in the second direction of the uppermost layer of the at least three conductive layers is connected to an interconnect line located above the at least three conductive layers through a contact plug.

12. The memory according to claim 1, wherein the at least three conductive layers are comprised of polysilicon.

13. The memory according to claim 1, wherein the bit line is comprised of metal.

14. The memory according to claim 1, wherein the columnar semiconductors are disposed in the first direction, and the bit line extends in the first direction.

15. The memory according to claim 1, wherein the semiconductor substrate has a source diffusion layer, and the columnar semiconductors are connected to the source diffusion layer.

16. The memory according to claim 15, wherein the source diffusion layer is common to the first and second blocks.

17. The memory according to claim 1, wherein the first driver is comprised of an FET, and a structure and a thickness of a gate electrode of the FET are the same as those of the second select gate line.

18. The memory according to claim 1, further comprising a second driver disposed on the other end in the second direction of the memory cell array.

19. The memory according to claim 1, further comprising a sense amplifier disposed on one end in the first direction of the memory cell array and connected to the bit line.