Non-volatile memory device having configurable page size

• US 8,068,365 B2
• Filed: 12/08/2008
• Issued: 11/29/2011
• Est. Priority Date: 02/04/2008
• Status: Active Grant

• Current Assignee: MOSAID Technologies Inc. (f/k/a Conversant Intellectual Property Management)
• Original Assignee: MOSAID Technologies Inc. (f/k/a Conversant Intellectual Property Management)
• Inventors: Kim, Jin-Ki
• Primary Examiner(s): AUDUONG, GENE NGHIA
• Application Number:
  US12/329,929
• Publication Number:
  US 20090196103A1
• Time in Patent Office: 1,086 Days
• Field of Search: 365/63, 365/185.11, 365/185.12, 365/185.23, 365/185.33, 365/230.06, 365/230.03
• US Class Current: 365/185.12
• CPC Class Codes: G11C 15/046 using non-volatile storage elements
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 16/08 Address circuits; Decoders; Word-line control circuits
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 16/16 for erasing blocks, e.g. arrays, words, groups
• CPC Class Codes: G11C 16/26 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 8/08 Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines
• CPC Class Codes: G11C 8/10 Decoders

Abstract

A flash memory device having at least one bank, where the each bank has an independently configurable page size. Each bank includes at least two memory planes having corresponding page buffers, where any number and combination of the memory planes are selectively accessed at the same time in response to configuration data and address data. The configuration data can be loaded into the memory device upon power up for a static page configuration of the bank, or the configuration data can be received with each command to allow for dynamic page configuration of the bank. By selectively adjusting a page size the memory bank, the block size is correspondingly adjusted.

Claims

1. A flash memory device comprising:

a memory bank having a plurality of planes, each of the plurality of planes having a page buffer for storing write data for programming to a corresponding plane and for storing read data from the corresponding plane; and

,

a page size configurator for selectively enabling combinations of the plurality of planes at the same time in response to configuration data and address data during a memory operation.

2. The flash memory device of claim 1, wherein each of the plurality of planes includes a dedicated row decoder for driving wordlines.

3. The flash memory device of claim 1, wherein the plurality of planes are organized as tiles, where each of the tiles includes a first plane and a second plane coupled to a shared row decoder for driving wordlines in the first plane and the second plane.

4. The flash memory device of claim 3, wherein the shared row decoder of each of the tiles selectively drives wordlines of at least one of the first plane and the second plane in response to row decoder enabling signals.

5. The flash memory device of claim 4, wherein the shared row decoder includes

a row driver for selectively passing row drive signals to the wordlines of the first plane in response to a first output voltage, and to the wordlines of the second plane in response to a second output voltage,

a block decoder for selectively providing a master output voltage as the first output voltage and the second output voltage in response to the row decoder enabling signals.

6. The flash memory device of claim 4, wherein the page size configurator includes

plane selectors for providing the row decoder enabling signals to corresponding shared row decoders in response to plane enabling signals and a tile enabling signal, and

a configuration decoder for decoding a plane address to provide the plane enabling signals and for decoding a tile address to provide the tile enabling signal, the plane enabling signals and the tile enabling signal having logic levels configurable in response to configuration data.

7. The flash memory device of claim 6, wherein the page size configurator further includes a configuration register for storing the configuration data.

8. The flash memory device of claim 6, wherein each of the plane selectors decodes the same plane enabling signals and different tile enabling signals.

9. The flash memory device of claim 8, wherein the configuration decoder includes

a plane decoding circuit enabled by a first bit of the configuration data for decoding the plane address and for driving one of the plane enabling signals to an active logic level, and

a tile decoding circuit enabled by a second bit of the configuration data for decoding the tile address and for driving one of the tile enabling signals to an active logic level.

10. The flash memory device of claim 9, wherein the plane decoding circuit drives both the plane enabling signals to the active logic level when disabled by the first bit of the configuration data, and the tile decoding circuit drives both the tile enabling signals to the active logic level when disabled by the second bit of the configuration data.

11. The flash memory device of claim 6, wherein each of the plane selectors decodes different pairs of plane enabling signals and different tile enabling signals.

12. The flash memory device of claim 11, wherein the configuration decoder includes

plane decoding circuits each receiving one bit of the configuration data for decoding the plane address, each of the plane decoding circuits driving one plane enabling signal of each of the different pairs of plane enabling signals to an active logic level when enabled by the corresponding one bit of the configuration data, and

a tile decoding circuit for decoding the tile address and driving one of the tile enabling signals to an active logic level when enabled by another bit of the configuration data.

13. The flash memory device of claim 4, wherein the memory bank includes N tiles, where N is an integer number greater than 1.

14. The flash memory device of claim 13, wherein the page size configurator includes

N plane selectors for providing N pairs of row decoder enabling signals to corresponding N shared row decoders in response to plane enabling signals and N tile enabling signals, and

a configuration decoder for decoding a plane address to provide the plane enabling signals and for decoding a tile address to provide the N tile enabling signals, the plane enabling signals and the N tile enabling signals having logic levels configurable in response to configuration data.

15. The flash memory device of claim 14, wherein the configuration decoder includes

one plane decoding circuit enabled by a first bit of the configuration data for decoding the plane address and driving one of the plane enabling signals to an active logic level, each of the N plane selectors receiving the same plane enabling signals, and

a tile decoding circuit enabled by a second bit of the configuration data for decoding the tile address and driving one of the N tile enabling signals to an active logic level.

16. The flash memory device of claim 14, wherein the plane enabling signals include N pairs of plane enabling signals, and the configuration decoder provides includes

N plane decoding circuits each decoding the plane address and driving one of the N pairs of plane enabling signals to an active logic level when enabled by a corresponding bit of the configuration data, each of the N plane selectors receiving one of the N pairs of plane enabling signals, and

a tile decoding circuit for decoding the tile address and driving one of the N tile enabling signals to an active logic level when enabled by another bit of the configuration data.

17. A method for accessing a memory bank having M planes, where M is an integer greater than 1, comprising:

receiving configuration data corresponding to a page size, the page size corresponding to between 1 and the M planes being simultaneously accessed during a memory operation;

logically configuring decoding circuits with the configuration data;

generating plane enabling signals with the decoding circuits in response to address data; and

,

enabling row decoder circuits in response to the plane enabling signals for simultaneously driving wordlines of the 1 to M planes.

18. The method of claim 17, wherein receiving includes receiving a command for executing one of a read, program and erase operation, the command including an operation code corresponding to the memory operation and the configuration data.

19. The method of claim 17, wherein receiving includes loading a configuration register with the configuration data.

20. The method of claim 19, wherein loading includes loading the configuration register with the configuration data during a power up operation.

21. The method of claim 19, wherein loading includes loading the configuration register with the configuration data provided in a dedicated command received before or after a command including an operation code for executing the memory operation.

22. The method of claim 17, wherein the address data includes plane address data, and logically configuring includes enabling plane decoding circuits with the configuration data to decode the plane address data, and generating includes driving selected plane enabling signals to an active logic level corresponding to the plane address data with the plane decoding circuits.

23. The method of claim 22, wherein logically configuring includes disabling the plane decoding circuits from decoding the plane address data, and generating includes driving all the plane enabling signals to an active logic level.

24. The method of claim 23, wherein the M planes are organized as tiles, where each of the tiles includes a pair of planes sharing the row decoder circuits.

25. The method of claim 24, wherein enabling includes providing row decoder enabling signals to the row decoder circuits corresponding to each of the tiles in response to the plane enabling signals when tile enabling signals are at an active logic level.

26. The method of claim 25, wherein the address data includes tile address data, logically configuring includes enabling tile decoding circuits with the configuration data to decode the tile address data, and generating includes driving selected tile enabling signals to an active logic level corresponding to the tile address data with the tile decoding circuits.

27. The method of claim 26, wherein logically configuring includes disabling the tile decoding circuits from decoding the tile address data, and generating includes driving all the tile enabling signals to the active logic level.