Shared memory architecture in GPS signal processing
First Claim
1. A processor in a GPS signal receiver having a first mode of operation and a second mode of operation, comprising:
- a plurality of correlators, wherein the number of correlators that are active during the first mode of operation is greater than the number of correlators that are active during the second mode of operation, and wherein each correlator (1) receives a predetermined code and an input data stream representing digitized signals received from OPS satellites, and (2) provides an output data stream representing a product of the input data stream and the predetermined code, offset by a code phase selected for that correlator;
an accumulator which receives the output data streams of the correlators and which provides, for each data stream, a corresponding integration sum over a predetermined time period; and
a memory circuit which receives and stores the integration sums from the accumulator wherein, during the second mode, memory space allocated for storing the integration sums corresponding to data streams from correlators that are active during the first mode, but not active during the second mode, are reallocated for use other than storing integration sums.
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Abstract
A shared memory architecture for a GPS receiver, wherein a processing memory is shared among the different processing functions, such as the correlator signal processing, tracking processing, and other applications processing. The shared memory architecture within the GPS receiver provides the memory necessary for signal processing operations, such as the massively parallel processing, while conserving memory cost by re-using that same memory for other GPS and non-GPS applications. The shared memory architecture for a GPS receiver provided in accordance with the principles of this invention thereby significantly minimize the costly memory requirement often required of extremely fast signal acquisition of a GPS receiver.
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Citations
18 Claims
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1. A processor in a GPS signal receiver having a first mode of operation and a second mode of operation, comprising:
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a plurality of correlators, wherein the number of correlators that are active during the first mode of operation is greater than the number of correlators that are active during the second mode of operation, and wherein each correlator (1) receives a predetermined code and an input data stream representing digitized signals received from OPS satellites, and (2) provides an output data stream representing a product of the input data stream and the predetermined code, offset by a code phase selected for that correlator; an accumulator which receives the output data streams of the correlators and which provides, for each data stream, a corresponding integration sum over a predetermined time period; and a memory circuit which receives and stores the integration sums from the accumulator wherein, during the second mode, memory space allocated for storing the integration sums corresponding to data streams from correlators that are active during the first mode, but not active during the second mode, are reallocated for use other than storing integration sums. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9)
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10. A method for efficient use of resources in a GPS signal receiver having a first mode of operation and a second mode of operation, comprising:
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providing a plurality of correlators, wherein the number of correlators that are active during the first mode of operation is greater than the number of correlators that are active during the second mode of operation; providing each active correlator a predetermined code and an input data stream representing digitized signals received from GPS satellites; providing from each active correlator an output data stream representing a product of the input data stream and the predetermined code offset by a code phase selected for that correlator; providing an accumulator which receives the output data streams of the active correlators and which provides, for each data stream, a corresponding integration sum over a predetermined time period; and storing in a memory circuit the integration sums from the accumulator; during the second mode, reallocating the memory space allocated for storing the integration sums corresponding to data streams from correlators that are active during the first mode, but not active during the second mode, for use other than storing integration sums. - View Dependent Claims (11, 12, 13, 14, 15, 16, 17, 18)
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Specification