Low-latency data decryption interface

• US 8,069,353 B2
• Filed: 06/19/2008
• Issued: 11/29/2011
• Est. Priority Date: 09/02/2004
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Pivonia, Gilad, Drehmel, Robert A., Kuesel, Jamie R., Beukema, Bruce L., Hall, William E., Shearer, Robert A.
• Primary Examiner(s): CERVETTI, DAVID GARCIA
• Application Number:
  US12/142,007
• Publication Number:
  US 20080288780A1
• Time in Patent Office: 1,258 Days
• Field of Search: 713/181, 380/210
• US Class Current: 713/181
• CPC Class Codes: G06F 21/72 in cryptographic circuits
• CPC Class Codes: H04L 2209/125 Parallelization or pipelining, e.g. for accelerating processing of cryptographic operations
• CPC Class Codes: H04L 63/123 received data contents, e.g. message integrity
• CPC Class Codes: H04L 9/06 the encryption apparatus using shift registers or memories for block-wise or stream coding, e.g. DES systems or RC4; Hash functions; Pseudorandom sequence generators

Abstract

Methods and apparatus for reducing the impact of latency associated with decrypting encrypted data are provided. Rather than wait until an entire packet of encrypted data is validated (e.g., by checking for data transfer errors), the encrypted data may be pipelined to a decryption engine as it is received, thus allowing decryption to begin prior to validation. In some cases, the decryption engine may be notified of data transfer errors detected during the validation process, in order to prevent reporting false security violations.

Claims

1. A system on a chip (SOC), comprising:

one or more processor cores;

a cache for holding data accessed by the one or more processor cores, including a received portion of a first data packet containing at least a portion of a block of encrypted data;

a decryption engine; and

a packet decoder configured to pipeline the received portion of the first data packet to the decryption engine to begin decryption of the encrypted data prior to receiving the complete first data packet and checking the complete first data packet for data transfer errors; and

further configured, after receiving remaining portions of the first data packet, to;

check the first data packet for data transfer errors using buffered portions of the encrypted data;

check for security violations with the decryption engine after decryption of the block of encrypted data; and

disregard any detected security violations in response to detecting data transfer errors.

2. A system on a chip (SOC), comprising:

one or more processor cores;

a cache for holding data accessed by the one or more processor cores, including a received portion of a first data packet containing at least a portion of a block of encrypted data;

a decryption engine; and

a packet decoder configured to pipeline the received portion of the first data packet to the decryption engine to begin decryption of the encrypted data prior to receiving the complete first data packet and checking the complete first data packet for data transfer errors; and

further configured, after receiving remaining portions of the first data packet, to;

check the first data packet for data transfer errors using buffered portions of the encrypted data;

check for security violations with the decryption engine after decryption of the block of encrypted data;

disregard any detected security violations in response to detecting data transfer errors; and

notify the decryption engine in response to detecting data transfer errors.

3. A system on a chip (SOC), comprising:

one or more processor cores;

a cache for holding data accessed by the one or more processor cores, including a received portion of a first data packet containing at least a portion of a block of encrypted data;

a decryption engine; and

a packet decoder configured to pipeline the received portion of the first data packet to the decryption engine to begin decryption of the encrypted data prior to receiving the complete first data packet and checking the complete first data packet for data transfer errors; and

further configured, after receiving remaining portions of the first data packet, to;

check the first data packet for data transfer errors using buffered portions of the encrypted data;

check for security violations with the decryption engine after decryption of the block of encrypted data;

disregard any detected security violations in response to detecting data transfer errors; and

buffer received portions of a second data packet containing non-encrypted data prior to completion of decryption of the encrypted data contained in the first data packet.

4. The SOC of claim 3, wherein the packet decoder is further configured to pass the non-encrypted data to the cache prior to completion of decryption of the encrypted data contained in the first data packet.

5. The SOC of claim 4, further comprising circuitry for merging decrypted data from the decryption engine to be passed to the cache with the non-encrypted data.