Method for debugging reconfigurable architectures

• US 8,069,373 B2
• Filed: 01/15/2009
• Issued: 11/29/2011
• Est. Priority Date: 09/03/2001
• Status: Active Grant

• Current Assignee: Scientia Sol Mentis AG (PACT XPP Schweiz AG)
• Original Assignee: Maren Krass, Thomas Richter
• Inventors: Vorbach, Martin
• Primary Examiner(s): CHU, GABRIEL L
• Application Number:
  US12/354,590
• Publication Number:
  US 20090150725A1
• Time in Patent Office: 1,048 Days
• Field of Search: None
• US Class Current: 714/38.1
• CPC Class Codes: G06F 11/26 Functional testing
• CPC Class Codes: G06F 11/267 Reconfiguring circuits for testing, e.g. LSSD, partitioning
• CPC Class Codes: G06F 11/3656 using a specific debug interface
• CPC Class Codes: G06F 15/7867 with reconfigurable architecture
• CPC Class Codes: G06F 9/30036 Instructions to perform operations on packed data, e.g. vector, tile or matrix operations

Abstract

A method for debugging reconfigurable hardware is described. According to this method, all necessary debug information is written in each configuration cycle into a memory, which is then analyzed by the debugger.

Claims

1. A method for debugging a program running on reconfigurable hardware, comprising:

writing debug information into a memory in each of a plurality of configuration cycles;

analyzing, by a debugger, the debug information;

loading a configuration, wherein the loading is performed during the debugging and responsive to occurrence of a debugging condition that indicates that information, regarding one of the configuration cycles, is needed; and

using the loaded configuration, reading the debug information out of the memory.

2. The method as recited in claim 1, further comprising:

altering a configuration to be debugged before the debugging in such a way that information not needed in normal non-debugging execution is stored in a memory.

3. The method as recited in claim 1, further comprising:

writing the debug information into a debugging unit or a debugging configuration.

4. A method for debugging a program running on reconfigurable hardware, comprising:

in each of a plurality of configuration cycles, configuring at least a portion of the reconfigurable hardware according to configurations defined by the program;

writing debug information into a memory in each of the plurality of configuration cycles;

analyzing, by a debugger, at least some of the debug information; and

at least partially slowing down or stopping a clock pulse frequency for readout.

5. The method as recited in claim 4, wherein the at least partially slowing down and stopping the clock pulse is performed responsive to completion of each of a plurality of processing steps of a configuration cycle.

6. A method for debugging a program running on reconfigurable hardware, comprising:

in each of a plurality of configuration cycles, configuring at least a portion of the reconfigurable hardware according to configurations defined by the program;

writing debug information into a memory in each of the plurality of configuration cycles;

analyzing, by a debugger, at least some of the debug information; and

simulating one of the plurality of configuration cycles according to readout of relevant information or according to previously available information.

7. The method as recited in claim 6, wherein the simulating includes outputting simulated values of each of at least one configurable element of the reconfigurable hardware determined for the simulated configuration cycle.

8. A reconfigurable device, comprising:

a field of configurable elements, the field including at least one of coarse-grained logic and arithmetic units;

a debugging arrangement for debugging a program running on the reconfigurable device, the debugging arrangement including a memory, wherein the debugging arrangement is adapted to;

write debug information into the memory in each of a plurality of configuration cycles in which one or more of the configurable elements is configured;

load a configuration, wherein the loading is performed during a debugging procedure and responsive to occurrence of a debugging condition that indicates that information, regarding one of the configuration cycles, is needed; and

using the loaded configuration, reading the debug information out of the memory; and

an analysis device adapted to analyze the debug information.

9. The device as recited claim 8, wherein the memory is a dual-ported RAM having a first input for information to be saved from the field and a second input for readout of information into the analysis device.

10. A method for debugging a program running on hardware including modules that are reconfigurable in a configuration cycle with respect to at least one of function and interconnection, comprising:

in each of at least a subset of a plurality of configuration cycles performed during the running of the program and for which debug information is to be obtained, at least a subset of the reconfigurable hardware modules being reconfigured in each of the configuration cycles with respect to the at least one of function and interconnection;

writing debug information into a memory; and

reading out of the memory the debug information for use by a debugger; and

analyzing by the debugger the debug information.

11. The method of claim 10, further comprising:

altering a configuration to be debugged before the debugging in such a way that information not needed in normal non-debugging execution is stored in a memory.

12. The method of claim 11, further comprising:

writing the debug information into a debugging unit or a debugging configuration.

13. The method of claim 11, further comprising:

at least partially slowing down or stopping a clock pulse frequency for readout.

14. The method of claim 10, further comprising:

at least partially slowing down or stopping a clock pulse frequency for readout.

15. The method of claim 14, further comprising:

writing the debug information into a debugging unit or a debugging configuration.

16. The method of claim 15, further comprising:

performing a cycle process of a configuration to be debugged, step by step.

17. The method of claim 10, further comprising:

performing a cycle process of a configuration to be debugged, step by step.

18. The method of claim 17, further comprising:

at least partially slowing down or stopping a clock pulse frequency for readout.

19. The method as recited in any of claims 10-18, further comprising:

simulating a configuration to be debugged according to readout of relevant information or according to previously available information.

20. A dynamically reconfigurable device, comprising:

a field of dynamically configurable elements, the field including at least one of coarse-grained logic and arithmetic units; and

a debugging arrangement to debug a program while executed on the field of configurable elements, wherein the debugging arrangement includes a memory to store information relevant to debugging during or at an end of a working step of the field of dynamically configurable elements;

wherein, in each of at least a subset of a plurality of configuration cycles (a) performed during execution of the program on the field of configurable elements, (b) during which at least a portion of the field of configurable elements are reconfigured with respect to at least one of function and interconnection, and (c) for which the information relevant to debugging is to be obtained, the debugging arrangement is configured to;

write the information relevant to debugging to the memory; and

read the information relevant to debugging out of the memory for debugging.

21. The device as recited in claim 20, wherein the memory is a dual-ported RAM having a first input for information to be saved from the field and a second input for readout of information into an analysis device.

22. A method for debugging a program running on hardware including modules that are reconfigurable in a configuration cycle with respect to at least one of function and interconnection, a plurality of configuration cycles being performed for the running of the program, at least a subset of the reconfigurable hardware modules being reconfigured in each of the plurality of configuration cycles with respect to the at least one of function and interconnection, the method comprising:

for at least a subset of the plurality of configuration cycles which occurs during a debugging operation;

following a first of the subset of the plurality of configuration cycles, prior to each subsequent one of the subset of the plurality of configuration cycles, transferring debug information from the reconfigurable modules into a memory;

reading out of the memory the debug information for use by a debugger; and

analyzing by the debugger the debug information.