Method and apparatus for evaluating and optimizing a signaling system

• US 8,069,378 B2
• Filed: 06/14/2010
• Issued: 11/29/2011
• Est. Priority Date: 02/02/2001
• Status: Expired due to Term

• Current Assignee: Rampart Asset Management LLC
• Original Assignee: Rambus Inc.
• Inventors: Stonecypher, William Franklin, Zerbe, Jared, Chau, Pak Shing
• Primary Examiner(s): TRIMMINGS, JOHN P
• Application Number:
  US12/815,382
• Publication Number:
  US 20100251040A1
• Time in Patent Office: 533 Days
• Field of Search: None
• US Class Current: 714/715
• CPC Class Codes: G01R 31/31703 Comparison aspects, e.g. signature analysis, comparators concerning scan tests G01R31/318566; concerning testers G01R31/3193
• CPC Class Codes: G01R 31/31713 Input or output interfaces for test, e.g. test pins, buffers for scan test G01R31/318572
• CPC Class Codes: G01R 31/31716 Testing of input or output with loop-back
• CPC Class Codes: G01R 31/31717 Interconnect testing by scan techniques see G01R31/31855
• CPC Class Codes: G01R 31/3183 Generation of test inputs, e.g. test vectors, patterns or sequences
• CPC Class Codes: G01R 31/31855 Interconnection testing, e.g. crosstalk, shortcircuits
• CPC Class Codes: G01R 31/318577 AC testing, e.g. current testing, burn-in
• CPC Class Codes: G01R 31/3187 Built-in tests
• CPC Class Codes: G06F 11/221 to test buses, lines or interfaces, e.g. stuck-at or open line faults
• CPC Class Codes: G06F 11/26 Functional testing
• CPC Class Codes: G06F 13/423 with synchronous protocol
• CPC Class Codes: G11C 29/02 Detection or location of defective auxiliary circuits, e.g. defective refresh counters
• CPC Class Codes: G11C 29/022 in I/O circuitry
• CPC Class Codes: G11C 29/025 in signal lines
• CPC Class Codes: G11C 29/40 using compression techniques
• CPC Class Codes: H04B 1/04 Circuits
• CPC Class Codes: H04B 1/16 Circuits
• CPC Class Codes: H04B 17/0085 using test signal generators
• CPC Class Codes: H04B 3/32 Reducing cross-talk, e.g. by compensating
• CPC Class Codes: H04L 1/0001 Systems modifying transmission characteristics according to link quality, e.g. power backoff adaptive data allocation for multicarrier modulation H04L5/0044; controlling transmission power for radio systems H04W52/04
• CPC Class Codes: H04L 1/242 : by comparing a transmitted test signal with a locally generated replica
• CPC Class Codes: H04L 1/243 : at the transmitter, using a loop-back
• CPC Class Codes: H04L 1/244 : test sequence generators
• CPC Class Codes: H04L 25/03885 : adaptive
• CPC Class Codes: H04L 5/1438 : Negotiation of transmission parameters prior to communication modified according to link quality H04L1/0001

Abstract

A method and apparatus for evaluating and optimizing a signaling system is described. A pattern of test information is generated in a transmit circuit of the system and is transmitted to a receive circuit. A similar pattern of information is generated in the receive circuit and used as a reference. The receive circuit compares the patterns. Any differences between the patterns are observable. In one embodiment, a linear feedback shift register (LFSR) is implemented to produce patterns. An embodiment of the present disclosure may be practiced with various types of signaling systems, including those with single-ended signals and those with differential signals. An embodiment of the present disclosure may be applied to systems communicating a single bit of information on a single conductor at a given time and to systems communicating multiple bits of information on a single conductor simultaneously.

Claims

1. An apparatus having (1) a normal mode where the apparatus is to process live data as part of a serial transmission or receipt pipeline and (2) a test mode where the apparatus is to generate test data including a pseudorandom bit sequence, the apparatus comprising:

a linear shift register having an input to, in the normal mode, receive the live data, the linear shift register also having an output and a storage capacity; and

circuitry to, in the test mode, feed back test data from the output of the linear shift register to the input of the linear shift register, while deterministically modifying at least some of the test data;

wherein the pseudorandom bit sequence has a data length greater than the storage capacity of the shift register.

2. The apparatus of claim 1, where the circuitry includes a logic element having:

a first logic element input to receive the test data from the output of the linear shift register; and

a second logic element input coupled to receive second data from an intermediate point of the shift register; and

a logic element output dependent on a logical combination of the test data from the output of the shift register and the second data, the logic element output coupled to the input of the linear shift register.

3. The apparatus of claim 1, where the circuitry performs an exclusive-OR operation between a copy of the test data from the shift register and a bit stream from another location, to generate data fed back to the input of the linear shift register.

4. The apparatus of claim 1, where the linear shift register includes a chain of flip-flops.

5. The apparatus of claim 1, where the linear shift register includes a first data storage element and a second data storage element, each operable in the normal mode to shift interleaved bits and each operable in the test mode to generate bits of the pseudorandom bit sequence.

6. The apparatus of claim 5, where:

each of the first and second data storage elements includes a respective linear shift register;

in the test mode, an output from each one of the respective linear shift registers is coupled to an input of the other of the respective linear shift registers; and

in the test mode, the circuitry modifies data output from at least one of the respective linear shift registers in accordance with second data from an intermediate point within one of the respective linear shift registers.

7. The apparatus of claim 6, where the first and second data storage elements are used in the normal mode to process even and odd bits of a serial sequence.

8. The apparatus of claim 6, where the circuitry includes a logic element having:

a first logic element input coupled to an output of one of the respective linear shift registers; and

a second logic element input coupled to receive a bit stream from an intermediate point within one of the respective linear shift registers; and

a logic element output coupled to the input of one of the respective linear shift registers.

9. The apparatus of claim 8, where the circuitry includes two instances of the logic element, each instance performing an exclusive-or function between data output from an associated one of the respective linear shift registers and a data stream from an approximate midpoint within one of the respective linear shift registers, and responsively outputting data to an input of the other of the respective linear shift registers.

10. The apparatus of claim 5, further comprising a multiplexer coupled to an output of each of the first and second data storage elements, the multiplexer controlled in at least the normal mode to alternate between the data storage elements to transmit the interleaved bits.

11. The apparatus of claim 1, embodied in a transmit circuit, the linear shift register used for parallel to serial conversion of and transmission of the live data during the normal mode.

12. The apparatus of claim 1, embodied in a receive circuit, the linear shift register used for receipt of and for serial to parallel conversion of data during the normal mode.

13. The apparatus of claim 12, embodied in each of a transmit circuit and the receive circuit of a signaling system, the linear shift register to perform parallel to serial conversion in the transmit circuit and to perform serial to parallel conversion in the receive circuit, the receive circuit further comprising a comparison circuit to compare a repeating pattern transmitted from the transmit circuit with a repeating pattern generated by the receive circuit.

14. The apparatus of claim 13, further comprising a circuit to vary relative timing of the transmit circuit and the receive circuit, to synchronize the repeating pattern transmitted by the transmit circuit with the repeating pattern generated by the receive circuit.

15. The apparatus of claim 13, where the linear shift register of each of the transmit circuit and the receive circuit includes an odd data storage element and an even data storage element, each of the odd data storage elements and the even data storage elements in the normal mode to process respective alternating bits of live data and in the test mode to respectively generate even and odd bits of the pseudorandom bit sequence.

16. The apparatus of claim 1, embodied in one of a transmit circuit or a receive circuit, the apparatus further comprising a signaling pad coupled to a transmission medium, the apparatus in the test mode to create the pseudorandom bit sequence for use in testing signaling over the transmission medium.

17. The apparatus of claim 1, where the linear shift register is initialized in the test mode via a parallel load input.

18. The apparatus of claim 17, further comprising at least one signaling pad coupled to a transmission medium, the transmission medium to convey differential signaling.

19. The apparatus of claim 1, further comprising means varying a signal parameter associated with the pseudorandom bit sequence over multiple repetitions of the pseudorandom bit sequence.

20. The apparatus of claim 19, embodied in a transmit circuit, where the means varies at least one of phase of transmit timing or a voltage level associated with transmission.

21. The apparatus of claim 19, embodied in a receive circuit, where the means varies at least one of phase of sampling or threshold voltage used in sampling of a repeating pattern sent over the transmission medium by a remote transmitter.

22. The apparatus of claim 21, where the repeating pattern is generated in the receive circuit in absence of transmission of a seed pattern to the receive circuit.

23. A system, comprising:

a transmit circuit having a transmit linear shift register and a test loop to generate a transmit pattern based on a repeated pseudorandom bit sequence, the pseudorandom bit sequence generated by the transmit linear shift register having a greater bit length than a capacity of the transmit linear shift register; and

a receive circuit having

a receive linear shift register and a test loop to generate a receive pattern based on a repeated pseudorandom bit sequence, the pseudorandom bit sequence generated by the receive linear shift register having greater bit length than the receive linear shift register, and

a circuit to compare the transmit pattern with the receive pattern;

where the transmit shift register and the receive shift register are used in a normal mode for serial transmission of live data between the transmit circuit and the receive circuit, and in a test mode for respective generation of the transmit pattern and the receive pattern.

24. The system of claim 23, where the transmit circuit in the test mode seeds the receive circuit with a seed pattern to generate the pseudorandom bit sequence using the receive linear shift register.

25. The system of claim 23, where the receive circuit is not preloaded with information to synchronize its pattern with that of the transmit circuit.

26. The system of claim 23, where each of the transmit circuit and the receive circuit includes means for, in the test mode, providing feedback from the respective linear shift register modified in a deterministic manner to generate an input to the respective linear shift register.

27. A method, comprising:

using a linear shift register in a normal mode to perform one of the serial transmission or the serial receipt of live data; and

using the linear shift register in a test mode to generate test data including a pseudorandom bit sequence having a length greater than an instantaneous bit capacity of the shift register, and using a feedback path to provide an input to the linear shift register based on an output of the linear shift register.

28. The method of claim 27, where using the linear shift register to provide the input includes modifying data from the output of the linear shift register in a deterministic manner as part of feedback path to provide the input.

29. The method of claim 27, where using the linear shift register in the normal mode includes using the linear shift register in a transmitter for the serial transmission of the live data to a remote receiver and in the test mode for the serial transmission of the pseudorandom bit sequence to the remote receiver.

30. The method of claim 29, where the pseudorandom bit sequence is a first pseudorandom bit sequence, the method further comprising in the remote receiver, in the test mode:

receiving the first pseudorandom bit sequence;

using a second linear shift register to generate a second pseudorandom bit sequence; and

comparing the first pseudorandom bit sequence with the second pseudorandom bit sequence.

31. The method of claim 30, where the transmitter and the remote receiver are coupled via a transmission medium, the method further comprising in the test mode performing one of:

in the transmitter, varying a signal transmission parameter to perform testing of the transmission medium;

or

in the remote receiver, varying a sampling parameter to perform testing of the transmission medium.

32. The method of claim 27, where using a linear shift register to generate the pseudorandom bit sequence includes logically combining a bit stream with the output of the linear shift register to generate an input to the linear shift register.

33. The method of claim 32, where logically combining includes performing an exclusive OR function.

34. The method of claim 27, further comprising producing the pseudorandom bit sequence as a repeating pattern.