Semiconductor circuit

• US 8,071,438 B2
• Filed: 09/02/2010
• Issued: 12/06/2011
• Est. Priority Date: 06/24/2003
• Status: Expired due to Fees

• Current Assignee: BeSang Inc.
• Original Assignee: BeSang Inc.
• Inventors: Lee, Sang-Yun
• Primary Examiner(s): Le, Thao P.
• Application Number:
  US12/874,866
• Publication Number:
  US 20110053332A1
• Time in Patent Office: 460 Days
• Field of Search: 438/239
• US Class Current: 438/239
• CPC Class Codes: H01L 21/2007 Bonding of semiconductor wafers to insulating substrates or to semiconducting substrates using an intermediate insulating layer H01L21/2011 takes precedence; bonding of semiconductor wafers to semiconductor wafers for junction formation H01L21/187
• CPC Class Codes: H01L 21/8221 Three dimensional integrated circuits stacked in different levels
• CPC Class Codes: H01L 2224/291 with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
• CPC Class Codes: H01L 2224/8385 using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
• CPC Class Codes: H01L 24/29 of an individual layer connector
• CPC Class Codes: H01L 24/83 using a layer connector
• CPC Class Codes: H01L 27/0688 Integrated circuits having a three-dimensional layout
• CPC Class Codes: H01L 2924/01006 Carbon [C]
• CPC Class Codes: H01L 2924/01013 Aluminum [Al]
• CPC Class Codes: H01L 2924/01015 Phosphorus [P]
• CPC Class Codes: H01L 2924/01033 Arsenic [As]
• CPC Class Codes: H01L 2924/01042 Molybdenum [Mo]
• CPC Class Codes: H01L 2924/01073 Tantalum [Ta]
• CPC Class Codes: H01L 2924/01074 Tungsten [W]
• CPC Class Codes: H01L 2924/07802 not being an ohmic electrical conductor
• CPC Class Codes: H01L 2924/13091 Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
• CPC Class Codes: H01L 2924/14 Integrated circuits
• CPC Class Codes: H01L 2924/19041 being a capacitor
• CPC Class Codes: H01L 2924/19042 being an inductor
• CPC Class Codes: H01L 2924/19043 being a resistor

Abstract

A semiconductor memory device includes a substrate and an interconnect region carried by the substrate. A donor layer is coupled to the interconnect region through a bonding interface. An electronic device is formed with the donor layer, wherein the electronic device is formed after the bonding interface is formed. A capacitor is connected to the electronic device so that the electronic device and capacitor operate as a dynamic random access memory device.

Claims

1. A method of forming a semiconductor circuit, comprising:

providing a carrier substrate which carries an interconnect region;

providing a donor layer coupled to a donor substrate with a detach layer;

coupling the donor layer to the carrier substrate through a metal bonding layer positioned between the donor layer and interconnect region;

decoupling the donor substrate from the detach layer so the donor layer is carried by the carrier substrate; and

forming a first electronic device with the donor layer.

2. The method of claim 1, wherein the interconnect region includes a refractory metal.

3. The method of claim 1, wherein the first electronic device is formed with the donor layer after the donor layer is coupled to the carrier substrate.

4. The method of claim 1, wherein the step of coupling a donor layer to the substrate includes forming a metal bonding interface.

5. The method of claim 1, wherein the donor layer consists essentially of a semiconductor material before the donor layer is coupled to the carrier substrate.

6. The method of claim 1, further including forming a capacitor connected to the first electronic device.

7. The method of claim 6, wherein the capacitor is formed after the donor layer is coupled to the substrate.

8. The method of claim 1, wherein the first electronic device operates as a static random access memory device.

9. The method of claim 1, wherein the first electronic device operates as a non-volatile memory device.

10. The method of claim 1, wherein the detach layer includes porous semiconductor material.

11. The method of claim 1, wherein the detach layer includes dielectric material.

23. The method of claim 1, wherein the metal bonding layer includes a metal-to-metal bonding interface.

24. The method of claim 1, wherein the metal bonding layer is spaced from the carrier substrate by the interconnect region.

25. The method of claim 1, wherein the interconnect region includes a metal via connected to the metal bonding layer.

26. The method of claim 1, wherein the carrier substrate includes a second electronic device in communication with the first electronic device through an interconnect which includes metal.

27. The method of claim 26, wherein the interconnect extends above and below the metal bonding layer.

28. The method of claim 1, further including forming the metal bonding layer on the interconnect region.

29. The method of claim 1, further including forming the metal bonding layer on the donor layer.

30. The method of claim 1, wherein the metal bonding layer includes a first metal layer formed on the interconnect region and a second metal layer formed on the donor layer.

31. The method of claim 1, wherein the step of providing the donor layer includes forming the donor layer so it has a uniform doping concentration.

32. The method of claim 1, wherein the step of providing the donor layer includes forming the donor layer so it has a non-uniform doping concentration.

12. A method of forming a semiconductor circuit, comprising:

providing a carrier substrate which carries an interconnect region;

providing a donor layer coupled to a donor substrate with a detach layer;

coupling the donor layer to the carrier substrate by forming a metal-to-metal bonding interface;

decoupling the donor substrate from the detach layer so the donor substrate is carried by the carrier substrate; and

forming a first electronic device with the donor layer after the bonding interface is formed.

13. The method of claim 12, wherein the donor layer does not include a second electronic device before the bonding interface is formed.

14. The method of claim 12, wherein the donor layer consists essentially of a semiconductor material before the bonding interface is formed.

15. The method of claim 12, wherein a portion of the donor layer between the electronic device and bonding interface consists essentially of semiconductor material.

16. The method of claim 12, further including forming a capacitor connected to the electronic device.

17. The method of claim 16, wherein the capacitor is formed after the bonding interface.

18. The method of claim 16, wherein the electronic device and capacitor operate as a dynamic random access memory cell.

19. The method of claim 12, wherein the electronic device operates as a static random access memory device.

20. The method of claim 12, wherein the electronic device operates as a non-volatile memory device.

21. The method of claim 12, wherein the detach layer includes porous semiconductor material.

22. The method of claim 12, wherein the detach layer includes dielectric material.

33. A method of forming a semiconductor circuit, comprising:

providing a carrier substrate which carries an interconnect region having a metal via;

providing a donor layer coupled to a donor substrate with a detach layer;

coupling the donor layer to the carrier substrate through a metal bonding layer spaced from the carrier substrate by the interconnect region; and

decoupling the donor substrate from the detach layer so the donor layer is carried by the carrier substrate.

34. The method of claim 33, wherein the metal via includes a refractory metal.

35. The method of claim 33, wherein the metal via and metal bonding layer are in communication with each other.

36. The method of claim 33, wherein the metal via and metal bonding layer are connected together.

37. The method of claim 33, wherein the detach layer includes porous semiconductor material.

38. The method of claim 33, wherein the metal bonding layer includes a metal-to-metal bonding interface.

39. The method of claim 33, wherein the metal bonding layer includes a first metal layer formed on the interconnect region and a second metal layer formed on the donor layer.