Display device and method of manufacturing the same

• US 8,071,985 B2
• Filed: 09/14/2007
• Issued: 12/06/2011
• Est. Priority Date: 09/14/2006
• Status: Active Grant

• Current Assignee: Japan Display West Incorporated (Japan Display Incorporated)
• Original Assignee: Sony Corporation (Sony Group Corp.)
• Inventors: Sakurai, Toru, Morimoto, Yusaku, Umetani, Yutaka
• Primary Examiner(s): Mandala, Victor A
• Assistant Examiner(s): HARRISTON, WILLIAM A
• Application Number:
  US11/855,753
• Publication Number:
  US 20080067519A1
• Time in Patent Office: 1,544 Days
• Field of Search: 257/72, 349/38, 349/42, 349/43, 349/44
• US Class Current: 257/72
• CPC Class Codes: G02F 1/136213 Storage capacitors associated with the pixel electrode
• CPC Class Codes: H01L 27/1255 integrated with passive devices, e.g. auxiliary capacitors
• CPC Class Codes: H01L 27/1281 by using structural features to control crystal growth, e.g. placement of grain filters
• CPC Class Codes: H01L 29/04 characterised by their crystalline structure, e.g. polycrystalline, cubic or particular orientation of crystalline planes characterised by physical imperfections H01L29/30
• CPC Class Codes: H01L 29/78633 with a light shield

Abstract

The invention provides a display device having a thin film transistor and a storage capacitor storing a display signal applied to a pixel electrode through this thin film transistor on a substrate, where dielectric strength between electrodes forming the storage capacitor is enhanced for increasing the yield. In the storage capacitor, a lower storage capacitor electrode, a thin lower storage capacitor film, a polysilicon layer, an upper storage capacitor film and an upper storage capacitor electrode are layered. The polysilicon layer is formed by crystallization by laser annealing. The polysilicon layer of the storage capacitor is microcrystalline and thus the flatness of its surface is enhanced. The pattern of the polysilicon layer (storage capacitor electrode) is formed larger than the bottom portion of an opening, and the edge of its peripheral portion is located on a buffer film on the slant portion of the opening or on the buffer film on the outside of the opening.

Claims

1. A display device comprising:

a substrate;

a thin film transistor disposed on the substrate and configured to receive a display signal, the thin film transistor comprising;

(a) a light-shielding layer disposed on the substrate;

(b) a buffer film disposed on the light shielding layer, the buffer film having;

(i) an opening;

(ii) a bottom portion;

(iii) a top portion; and

(iv) a slant portion such that the bottom portion is smaller than the top portion;

(c) a first portion of a polysilicon layer disposed on the buffer film, the first portion of the polysilicon layer having;

(i) a surface;

(ii) protrusions formed on the surface; and

(iii) a first grain size;

(d) a gate insulation film disposed on the first portion of the polysilicon layer, the gate insulation film covering the protrusions; and

(e) a gate electrode disposed on the gate insulation film; and

a storage capacitor disposed on the substrate and configured to store the display signal supplied by the thin film transistor, the storage capacitor comprising;

(a) a lower storage capacitor electrode disposed on the substrate;

(b) a lower storage capacitor film disposed pn the buffer film, the lower storage capacitor film being;

(i) in contact with the lower storage capacitor electrode through the opening in the buffer film; and

(ii) thinner than the buffer film;

(c) a middle storage capacitor electrode disposed on the lower storage capacitor film, the middle storage capacitor;

(i) being formed of a second portion of the polysilicon layer;

(ii) having an edge portion;

(iii) being larger than the bottom portion of the buffer film such that the edge portion is located over the slant portion of the buffer film; and

(iv) having a second grain size which is smaller than the first grain size;

(d) an upper storage capacitor film disposed on the middle storage capacitor electrode; and

(e) an upper storage capacitor electrode disposed on the upper storage capacitor film.

2. The display device of claim 1, wherein the second grain size is smaller than a third grain size of the second portion of the polysilicon layer which is located on the slant portion.

3. The display device of claim 1, wherein:

(a) the middle storage capacitor electrode is larger than a bottom of the buffer film so that the entire edge portion of the middle storage capacitor electrode is located on the buffer film; and

(b) the second grain size is smaller than a third grain size of the second portion of the polysilicon layer which is along the edge portion of the middle storage capacitor electrode.

4. The display device of claim 1, wherein a sum of thicknesses of the buffer film and the lower storage capacitor film is 300 nm or more.

5. The display device of claim 2, wherein a sum of thicknesses of the buffer film and the lower storage capacitor film is 300 nm or more.

6. The display device of claim 3, wherein a sum of thicknesses of the buffer film and the lower storage capacitor film is 300 nm or more.

7. The display device of claim 1, wherein a thickness of the lower storage capacitor film is 100 nm or less.

8. The display device of claim 2, wherein a thickness of the lower storage capacitor film is 100 nm or less.

9. The display device of claim 3, wherein a thickness of the lower storage capacitor film is 100 nm or less.

10. The display device of claim 2, wherein the edge portion of the middle storage capacitor electrode does not overlap the upper storage capacitor electrode.

11. The display device of claim 3, wherein the edge portion of the middle storage capacitor electrode does not overlap the upper storage capacitor electrode.

12. A method of manufacturing a display device, comprising:

(a) forming a light-shielding layer and a lower storage capacitor electrode on a substrate;

(b) forming a buffer film on the light-shielding layer and the lower storage capacitor electrode, the buffer film having;

(i) a bottom portion;

(ii) a top portion; and

(iii) a slant portion such that the bottom portion is smaller that the top portion;

(c) forming an opening in the buffer film to expose at least partially the lower storage capacitor electrode;

(d) forming a lower storage capacitor film thinner than the buffer film on the exposed lower storage capacitor electrode;

(e) forming, after the formation of the lower storage capacitor film, an amorphous silicon layer on the buffer film and the lower storage capacitor electrode;

(f) transforming the amorphous silicon layer into a polysilicon layer by layer annealing while the amorphous silicon layer is exposed so that the polysilicon layer above the buffer film has protrusions on a surface thereof;

(g) forming a middle storage capacitor electrode by patterning the polysilicon layer, the middle storage capacitor;

(i) having an edge portion; and

(ii) being larger than the bottom portion of the buffer film such that the edge portion is located over the slant portion of the buffer film;

(h) forming a gate insulation film on the polysilicon layer and an upper storage capacitor film on the middle storage capacitor electrode; and

(i) forming a gate electrode on the gate insulation film and an upper storage capacitor electrode on the upper storage capacitor film.

13. The method of claim 12, wherein the storage capacitor electrode is formed so as to be larger than a bottom portion of the opening and have an edge located on the buffer film on an outside of the bottom portion.

14. The method of claim 12, wherein a sum of thicknesses of the buffer film and the lower storage capacitor film is 300 nm or more.

15. The method of claim 12, wherein a sum of thicknesses of the buffer film and the lower storage capacitor film is 300 nm or more.

16. The method of claim 13, wherein a sum of thicknesses of the buffer film and the lower storage capacitor film is 300 nm or more.

17. The method of claim 12, wherein a thickness of the lower storage capacitor film is 100 nm or less.

18. The method of claim 12, wherein a thickness of the lower storage capacitor film is 100 nm or less.

19. The method of claim 13, wherein a thickness of the lower storage capacitor film is 100 nm or less.