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Avalanche capability improvement in power semiconductor devices having dummy cells around edge of active area

  • US 8,072,000 B2
  • Filed: 04/29/2009
  • Issued: 12/06/2011
  • Est. Priority Date: 04/29/2009
  • Status: Active Grant
First Claim
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1. A vertical semiconductor power MOSFET device comprising a plurality of semiconductor power cells with each cell comprising a trenched gate surrounded by a source region with a first type conductivity in an active area encompassed in a body region with a second type conductivity above a drain region disposed on a bottom surface of a low-resistivity substrate with said first type conductivity, wherein said MOSFET cell further comprising:

  • an epitaxial layer of said first type conductivity over said substrate, said epitaxial layer having a lower doping concentration than the substrate;

    a first insulating layer serving as a gate oxide lining the inner surface of openings for said trenched gates;

    a second insulating layer functioning as a thick contact oxide interlayer covering top surface of the epitaxial layer;

    a plurality of trench source-body contacts filled with tungsten plugs and opened through the second insulating layer and extending into the body region;

    at least one dummy cell without said source region formed at the edge of said active area near by a gate metal pad and a gate metal runner;

    a source metal layer connected to the source regions and the body regions via the trench source-body contacts;

    a drain metal layer formed on a bottom surface of the substrate;

    a gate metal layer served as said gate metal runner and connected to said gate metal pad for wire bonding, said gate metal runner also serving as a metal field plate deposited over a deep guard ring of said second type conductivity in a termination area.

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