Polarity dependent switch for resistive sense memory
First Claim
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1. A memory unit, comprising:
- a resistive sense memory cell configured to switch between a high resistance state and a low resistance state upon passing a current through the resistive sense memory cell;
a semiconductor transistor in electrical connection with the resistive sense memory cell, the semiconductor transistor comprising a gate element formed on a substrate, the semiconductor transistor comprises a source contact and a bit contact, the gate element electrically connecting the source contact and the bit contact, the resistive sense memory cell electrically connected to the bit contact, the source contact being more heavily implanted with dopant material than the bit contact.
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Abstract
A memory unit includes a resistive sense memory cell configured to switch between a high resistance state and a low resistance state upon passing a current through the resistive sense memory cell and a semiconductor transistor in electrical connection with the resistive sense memory cell. The semiconductor transistor includes a gate element formed on a substrate. The semiconductor transistor includes a source contact and a bit contact. The gate element electrically connects the source contact and the bit contact. The resistive sense memory cell electrically is connected to the bit contact. The source contact is more heavily implanted with dopant material then the bit contact.
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Citations
20 Claims
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1. A memory unit, comprising:
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a resistive sense memory cell configured to switch between a high resistance state and a low resistance state upon passing a current through the resistive sense memory cell; a semiconductor transistor in electrical connection with the resistive sense memory cell, the semiconductor transistor comprising a gate element formed on a substrate, the semiconductor transistor comprises a source contact and a bit contact, the gate element electrically connecting the source contact and the bit contact, the resistive sense memory cell electrically connected to the bit contact, the source contact being more heavily implanted with dopant material than the bit contact. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 13, 14, 15)
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11. A memory unit, comprising:
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a resistive sense memory cell configured to switch between a high resistance state and a low resistance state upon passing a current through the resistive sense memory cell; a first switching device in electrical connection with the resistive sense memory cell, the first switching device comprising a first gate element formed on a substrate, the first switching device comprises a first source contact and a common bit contact, the first gate element electrically connecting the first source contact and the common bit contact, the resistive sense memory cell electrically connected to the common bit contact, the first source contact being more heavily implanted with dopant material than the common bit contact; and
a second switching device in electrical connection with the resistive sense memory cell, the second switching device comprising a second gate element formed on the substrate, the second switching device comprises a second source contact and the common bit contact, the second gate element electrically connecting the second source contact and the common bit contact, the resistive sense memory cell electrically connected to the common bit contact, the second source contact being more heavily implanted with dopant material than the common bit contact. - View Dependent Claims (12, 16, 17, 18)
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19. A select device comprising;
a semiconductor transistor comprising a gate element formed on a substrate, the semiconductor transistor comprises a source contact and a bit contact, the gate element electrically connecting the source contact and the bit contact, the source contact being more heavily implanted with dopant material than the bit contact. - View Dependent Claims (20)
Specification